Lead Software Engineer - Liberate

Reposted 25 Days Ago
Be an Early Applicant
Shanghai, Shanghai Municipality, Shanghai, CHN
In-Office
Junior
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and maintain EDA software for circuit simulation and analysis. Implement features in C/C++/TCL on Linux, work with SPICE-like simulators, and support flows for library characterization, IP design, static timing, power, and signal integrity. Collaborate with semiconductor experts and apply knowledge of Verilog/VHDL where needed.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The candidates should have two or more years of experiences in developing EDA software.

 Must be proficient in C, C++, TCL, and development in Linux/Unix.
 Knowledge on semiconductor device is strong plus.
 Experience with SPICE or SPICE-like circuit simulation is important.
 Knowledge of Verilog and VHDL is also highly desirable.
 Have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.
 Minimum Education Required / Minimum Experience Required : MS, EE, CS, Math or Physics 2
 Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math or Physics 3-5

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 2+ years developing EDA software
  • Proficiency in C
  • Proficiency in C++
  • Proficiency in TCL
  • Development experience in Linux/Unix
  • Experience with SPICE or SPICE-like circuit simulation
  • Good understanding of library characterization
  • Good understanding of IP design
  • Good understanding of static timing analysis flows
  • Good understanding of power analysis flows
  • Good understanding of signal integrity analysis flows
  • Minimum education: MS in EE, CS, Math, or Physics
  • Knowledge of Verilog
  • Knowledge of VHDL
  • Knowledge of semiconductor devices
  • Preferred: Ph.D. in EE, CS, Math, or Physics
  • Preferred: 3-5 years experience (preferred)

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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