Lead / Principal DFT Engineer
Fractile is building the silicon, systems and software to break through the memory wall, the fundamental hardware constraint standing between today's AI and what comes next.
The frontier of AI is no longer a research problem. The tasks AI can complete are doubling in complexity every six to seven months and the tokens required to complete them are scaling with it. Sequential reasoning, the kind that can't be parallelised away, means the internal clock speed of inference systems is the critical constraint. What stands between where we are today and the future potential of AI isn't smarter algorithms; it's the hardware to run them fast enough to matter.
Today's chips are hitting their wall. We're building the ones that don't.
Fractile is seeking to increase the clock speed of global progress, one chip at a time.
Key Responsibilities
- Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan)
- Set DFT strategy, methodology, flow and signoff criteria
- Drive integration of DFT tools and flows into the overall EDA environment
- Define hierarchical DFT approach for multi-core designs and large memory systems
- Define scan architecture, compression strategy, and ATPG approach
- Define memory test and repair strategy for large embedded RAM
- Establish power-aware and at-speed test strategies
- Work closely with RTL and physical design to ensure clean DFT integration and timing closure
- Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
- Mentor and guide DFT engineers
Required Experience
- Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years)
- Proven ownership of DFT architecture on at least one large tapeout
- Deep expertise in scan, compression, ATPG, and MBIST
- Experience with industry tools (Synopsys or Tessent)
- Strong understanding of clocking, resets, power domains, and physical constraints
- Experience with silicon bring-up, debug, and yield ramp
Profile
- Comfortable owning ambiguous, high-impact problems
- Balances architectural thinking with hands-on execution
- Sets direction while staying close to implementation details
About us:
• Founded 2022, we're 100+ people across London and Bristol, in the heart of the UK's frontier AI ecosystem, and growing fast.
• We offer competitive salaries, meaningful equity, and standard company benefits.
• We believe the hardest problems get solved by the broadest range of minds. We actively encourage applications from underrepresented groups in hardware and software engineering.
• Hybrid working; 2-3 days in our London and Bristol offices.
Export controls:
Our work involves technologies subject to UK and international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.
Skills Required
- Strong experience in DFT for complex ASIC/SoC designs
- Proven ownership of DFT architecture on at least one large tapeout
- Deep expertise in scan, compression, ATPG, and MBIST
- Experience with industry tools (Synopsys or Tessent)
- Strong understanding of clocking, resets, power domains, and physical constraints
- Experience with silicon bring-up, debug, and yield ramp
What We Do
Fractile is developing AI chips designed for efficient AI model inference, aiming to radically improve the speed and cost of running frontier AI models by eliminating memory bottlenecks.
