Jobs at Fractile

The Lead Physical Design Engineer will manage IC physical design implementations from synthesis to sign-off, leading a team and collaborating across functions to optimize performance and manufacturability while mentoring others in the process.

As a Senior System Architect, you will design system architectures for AI applications, ensuring integration and performance from concept to production by collaborating with hardware and software teams.

The Senior System Architect will define hardware architecture, oversee system design and integration, and ensure technical excellence across disciplines. Responsibilities include developing system roadmaps, collaborating with teams on designs, and mentoring for design discipline.

The Lead Physical Design Engineer will implement complex IC designs, collaborating across teams to optimize performance, power, and area while ensuring manufacturability and design integrity.

Lead and grow a 10+ engineer compiler team to build the compiler stack for a novel AI accelerator. Drive compiler architecture, IR design, lowering strategies and performance optimisation, collaborating closely with hardware, driver, runtime and ML teams to enable industry-leading LLM inference performance.

As a Physical Design Engineer, you will implement complex IC designs, optimize PPA metrics, and ensure design integrity while collaborating with cross-functional teams.

The Physical Design Engineer will implement ASIC/SoC designs, perform timing analysis, maintain design integrity, and collaborate with cross-functional teams.

Build developer-facing tooling, diagnostics, and workflows to run and optimise large language models on Fractile inference hardware. Create profiling/observability interfaces, quickstarts, docs, and examples. Advocate for external developer needs internally and collaborate with ML compiler, runtime, systems software, and silicon teams to shape APIs and abstractions.

The role involves taking high-performance PCBAs from prototype to production, focusing on manufacturing processes and quality metrics. It requires deep expertise in PCB design and factory operations, particularly with Taiwan partners.

Lead the end-to-end DFT architecture for a multi-core AI accelerator SoC, ensuring integration, compliance, and effective test strategies while mentoring a team.

Define and drive the architecture of compute engines, managing specifications, performance modelling, and collaborating with various teams to ensure optimal designs.

As a Processor Architect, you'll develop and drive the architecture of compute engines, working with multiple teams to optimize performance and efficiency while defining specifications and mentoring others.

Join cross-functional teams to develop low-level software for novel SoC platforms: write/debug Linux kernel drivers (Rust), optimize instruction-level compute kernels on RISC-V/ISA, build firmware for bare-metal/RTOS/embedded Linux, extend QEMU simulators, and perform hardware-software bring-up and low-level debugging from simulation to silicon.

The Senior Logical Design Engineer will develop and implement high-performance RTL designs, collaborating with cross-functional teams, ensuring compliance with documentation and standards.

The role involves designing and implementing digital systems, focusing on developing RTL designs for high-performance and power-efficient systems while collaborating with cross-functional teams.

The Senior Verification Engineer will lead pre-silicon RTL verification processes, build testbenches, and improve hardware workflows in a collaborative team focused on ML/AI IC products.

As a Silicon Verification Engineer, you will verify ML/AI IC products, ensuring high standards of functional quality while collaborating across teams.

As a Verification Engineer, you'll contribute to building ML/AI IC products, ensuring high standards of functional quality through collaboration on RTL verification.

The Senior Verification Engineer will lead RTL verification processes, collaborate across disciplines, and improve hardware development workflows while ensuring high-quality product specifications.

Build developer-facing tooling, SDKs, and interfaces to deploy, profile, and monitor large language models on Fractile inference hardware; write docs and tutorials; represent external developer needs; and collaborate closely with ML compiler, runtime, systems software, and silicon engineers to shape APIs and workflows.