- B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related field.
- 8+ years of experience in Physical Design, Power Integrity, or Signoff.
Key ResponsibilitiesTechnical Skills:
- Own full-chip and subsystem-level PDN signoff for complex SoCs.
- Define PDN signoff criteria across project milestones.
- Drive power integrity closure for functional, DFT, LBIST, capture, and stress modes.
- Lead package-aware IR/EM analysis and chip-package co-optimization.
- Define and review power grid architecture, bump planning, power switch strategy, and decap methodology.
- Drive Vmin, peak EM, dynamic IR, and thermal-aware analysis.
- Develop next-generation PDN signoff methodologies.
- Automate PDN flows using TCL/Python/Shell.
- Improve runtime, capacity, dashboarding, and regression infrastructure.
- Collaborate with EDA vendors (Ansys/Cadence/Synopsys) for feature enhancements and tool debug.
- Establish best practices and reusable signoff frameworks across projects.
- Work closely with Physical Design teams to drive PDN-aware floorplanning, placement, routing, and ECO solutions.
- Partner with DFT teams to optimize pattern power and capture-mode reliability.
- Collaborate with Package and Thermal teams on package RLC optimization and thermal correlation.
- Support silicon bring-up, debug, and correlation of pre-silicon versus post-silicon measurements.
- Provide technical risk assessment and mitigation plans.
- Drive closure of critical PDN hotspots with minimal PPA impact.
- Present signoff status to management and project stakeholders.
- Ensure on-time delivery for tapeout milestones.
- Lead reviews for high-risk blocks and top-level integrations.
- Mentor engineers and PDN owners across multiple projects.
- Define training content and technical roadmaps for the team.
- Lead technical reviews and establish signoff governance.
- Influence organizational PDN strategy and future technology direction.
#LI-DNI
Skills Required
- B.Tech or M.Tech in Electronics, Electrical Engineering, VLSI, or a related field
- 8+ years of experience in Physical Design, Power Integrity, or Signoff
NXP Semiconductors Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about NXP Semiconductors and has not been reviewed or approved by NXP Semiconductors.
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Retirement Support — Feedback suggests the 401(k) program is strong, with reports of a 100% match on the first 5% of base salary. This is seen as a solid pillar of the overall rewards package.
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Equity Value & Accessibility — An employee stock purchase plan with a 15% discount is highlighted as a meaningful benefit. This feature adds perceived long-term value beyond base pay.
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Healthcare Strength — Medical, dental, and vision coverage alongside HSA/FSA options and wellness incentives are described as comprehensive. These offerings contribute to a sense of robust core benefits.
NXP Semiconductors Insights
What We Do
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA
