Lead Design Engineer - Physical Design

Reposted 18 Days Ago
Be an Early Applicant
Beijing, CHN
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The role involves high-speed digital DDR and HBM IP physical implementation, scripting to enhance design flow, and project task completion.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the team:

Our team deliver many high-performance products based on the industry’s advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.

Job Responsibilities:

Focus on high speed digital DDR and HBM IP physical implementation, develop necessary scripts or tools to enhance current PD design flow.

Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

Job Requirement:

-MS in EE with at least 3 years relevant IC design experience

-Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.

-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.

-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.

-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • MS in EE
  • 3 years relevant IC design experience
  • Good physical design experience in digital implementation
  • Background in circuits, electronics, physics
  • Skilled in scripting language
  • Familiar with EDA tools

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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