Responsible for enabling Foundry PDK teams and Foundry Design Service teams to deploy signoff‑quality standard cell, IO, and memory libraries using Cadence Liberate Characterization Suite. This role focuses on library modeling methodology, characterization techfile development, and design‑ready reference flow enablement aligned with foundry signoff requirements.
Key Responsibilities – Foundry PDK Team Support- Support foundry PDK teams in development, validation, and maintenance of Liberate characterization techfiles for standard cell, IO, and memory libraries.
- Collaborate with foundry teams to define SPICE corner, PVT, and RC assumptions used for library signoff.
- Enable generation of signoff‑quality Liberty models (NLDM / CCS / CCSP) aligned with foundry requirements.
- Support characterization of timing, power, leakage, noise, and SI effects for advanced nodes.
- Assist foundry PDK qualification and IP vendor enablement through library quality checks and debugging.
- Work with foundry modeling and signoff teams to ensure consistency between library models and downstream STA, power, and reliability analysis.
- Develop and maintain design reference flows for standard cell, IO, and memory libraries used by foundry design service teams.
- Support integration of Liberate libraries into design implementation and signoff flows.
- Provide guidance on library usage, corner selection, and modeling trade‑offs for large‑scale SoC projects.
- Support characterization model selection for pre‑layout, post‑layout, ECO, and signoff stages.
- Assist design service teams in debugging timing, power, SI, and convergence issues related to library quality.
- Enable reusable and standardized library handoff flows across multiple design service projects.
Skills Required
- Experience with Cadence Liberate Characterization Suite
- Knowledge of library modeling methodology and characterization techfiles
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
