Front End ASIC RTL/Logic Design Engineer

Job Details:

Job Description:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Supports SoC customers to ensure high-quality integration and verification of the IP block.

• Drives quality assurance compliance for smooth IP-SoC handoff.

Qualifications:

• BS/MS or PhD in Electronics Engineering

• Strong in communication, leadership, investigation, problem solving & analytical skill

• Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments

• Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT. Knowledge scripting desirable

Job Type: Regular

Shift:Shift 1 (Malaysia)

Primary Location:Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.