Design Engineer I ( Synthesis/LEC/CLP )

Posted 2 Days Ago
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2 Locations
In-Office
Junior
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Supports ASIC design-flow execution, including logical equivalence checking, logic synthesis, low-power jobs, constraint reviews, status tracking, ECO scripting, and documentation. The role develops expertise in synthesis, LEC, and low-power design while using Tcl, Perl, Python, or Unix shell scripting. Candidates need an electronics or electrical engineering degree, basic ASIC-flow knowledge, scripting ability, and strong analytical and communication skills.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Location: Bangalore / Pune

Experience: 0–2 Years

BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

About the Role

We are looking for a Design Engineer to join our synthesis/LEC/CLP team, supporting execution-level tasks across the ASIC design flow. This is a strong opportunity for an engineer early in their career to build deep expertise in synthesis, Logical equivalence checking and low-power design.

Key Responsibilities
  • Assist in running and monitoring Logical Equivalence Checking (LEC), Logic Synthesis, and Conformal Low Power jobs across design blocks
  • Support constraint reviews, generation, and basic debug
  • Help track and document LEC & synthesis status across blocks.
  • Learn and apply power intent basics to support CLP sign-off tasks
  • Support ECO script writing and basic scripting tasks (Tcl/Perl/Python)
  • Maintain clean documentation of runs, issues, and findings.
Required Skills
  • 0–2 years of experience: internship or academic project experience with ASIC flows is a plus
  • Bachelor's/master’s degree in Electronics, Electrical Engineering
  • Basic understanding of the complete ASIC design flow.
  • Basic scripting skills (Python, Perl, Tcl, or Unix shell)
  • Strong analytical and problem-solving skills; eager to learn EDA tool flows
  • Good communication skills and ability to work well in a team
Preferred
  • Exposure to Cadence tools (Genus, Conformal) through coursework or internship
  • Basic understanding of digital logic design and computer architecture

Regards

K Madhu Prasad

[email protected]

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 0-2 years of experience; internship or academic ASIC-flow project experience is a plus
  • Bachelor's or master's degree in Electronics or Electrical Engineering
  • Basic understanding of the complete ASIC design flow
  • Basic scripting skills in Python, Perl, Tcl, or Unix shell
  • Strong analytical and problem-solving skills
  • Good communication skills and ability to work well in a team
  • Exposure to Cadence Genus and Conformal tools through coursework or internship
  • Basic understanding of digital logic design and computer architecture

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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