ASIC DFT Engineering Technical Leader | Scan, ATPG, MBIST

Posted 13 Days Ago
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2 Locations
In-Office
Expert/Leader
Cloud • Information Technology • Internet of Things • Professional Services • Software
The Role
Lead ASIC DFT efforts across front-end RTL and backend physical design to define DFT architecture, ATPG/BIST strategies, scan insertion, and test infrastructure. Drive verification, gate-level and timing simulations, post-silicon validation with ATE, and collaborate with vendors and stakeholders for timing closure and electrical/interface specifications.
Summary Generated by Built In
Meet the team:The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact:You will be in the Silicon One development organization as an ASIC Implementation Technical Lead  with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.  As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. Key Contributions:
  • Manages the definition, architecture and design of high performance ASICs
  • Owns applications or multiple complex functional areas
  • Oversees reusable code and its applications
  • Creates re-usable code that promotes efficiencies in new ways
  • Defines verification strategies
  • Coordinates with appropriate stakeholders to integrate into PD and DV flows
  • Owns infrastructure and testing environmens
  • Leads and designs the building blocks of multiple channels
  • Applies and drives the design methodology from conception to production
  • Influences and collaborates with teams to ensure specifications and requirements are met
  • Leads technical expertise of a physical design function
  • Interfaces with vendors and design leads on full chip timing closure, PI, and PV
  • Owns the full electrical planning and specifications of electrical interfaces
  • Develops multiple solutions, first test vehicles and performs verification and validation
Minimum Qualifications: 
  • Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12+ years of experience. 
  • Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan. 
  • Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,  
  • Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators. 
  • Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
  • Scripting skills: Tcl, Python/Perl. 

 

Preferred Qualifications: 
  • Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification 
  • DFT CAD development – Test Architecture, Methodology and Infrastructure
Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Skills Required

  • Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 12+ years of experience
  • Experience with JTAG protocols (p1500, p1687), scan insertion, BIST architectures including memory BIST and boundary scan
  • Experience with ATPG and EDA tools (TestMax, Tetramax, Tessent) and static timing analysis constraints development and timing closure
  • Experience with gate-level simulation including timing-based simulations using SDF and debugging with VCS or other simulators
  • Post-silicon validation and debug experience; ability to work with ATE engineers on pattern translation and validation
  • Scripting skills: Tcl, Python or Perl
  • Verilog design experience developing custom DFT logic and IP integration; familiarity with functional verification
  • DFT CAD development experience: Test architecture, methodology and infrastructure

Cisco Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cisco and has not been reviewed or approved by Cisco.

  • Healthcare Strength Comprehensive medical, dental, and vision coverage, mental health support via an EAP, and access to on-site or virtual health centers indicate robust healthcare offerings. Wellness programs, fitness resources, and specialized services further reinforce coverage depth.
  • Leave & Time Off Breadth Generous PTO, a global minimum for paid parental leave, and unique programs like company-wide recharge days and paid volunteer time expand time-away options. Additional offerings such as Critical Time Off and adoption assistance add flexibility for life events.
  • Equity Value & Accessibility Restricted stock units and a discounted employee stock purchase plan are meaningful elements of total compensation. The prominence of equity can materially augment overall pay packages alongside salary and bonuses.

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The Company
HQ: San Jose, CA
77,500 Employees
Year Founded: 1984

What We Do

Cisco (NASDAQ: CSCO) enables people to make powerful connections--whether in business, education, philanthropy, or creativity. Cisco hardware, software, and service offerings are used to create the Internet solutions that make networks possible--providing easy access to information anywhere, at any time. Cisco was founded in 1984 by a small group of computer scientists from Stanford University. Since the company's inception, Cisco engineers have been leaders in the development of Internet Protocol (IP)-based networking technologies. Today, with more than 71,000 employees worldwide, this tradition of innovation continues with industry-leading products and solutions in the company's core development areas of routing and switching, as well as in advanced technologies such as home networking, IP telephony, optical networking, security, storage area networking, and wireless technology. In addition to its products, Cisco provides a broad range of service offerings, including technical support and advanced services. Cisco sells its products and services, both directly through its own sales force as well as through its channel partners, to large enterprises, commercial businesses, service providers, and consumers.

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