The Role and Impact
Intel is seeking a passionate and skilled Analog Layout Design Engineer to join our diverse and inclusive team. As a critical contributor to our design ecosystem, you will drive the creation and optimization of complex layouts for analog signal circuits, ensuring that our designs meet stringent performance, area, and reliability requirements. Your work will directly impact Intel's cutting-edge technologies, enabling the development of innovative solutions that empower businesses and transform industries.
In this collaborative role, you will work with cross-functional teams, including analog circuit design, process technology, and package design, to deliver layouts that are efficient, robust, and aligned with our high standards of excellence. We welcome candidates from all backgrounds who are eager to contribute to groundbreaking advancements while expanding their expertise in layout methodologies.
What You’ll Do
Key responsibilities will include but not limited to:
- Design complex layouts of analog signal circuits based on detailed design specifications.
- Conduct a comprehensive set of design verification checks, including process design rules, electron migration, voltage drop (IR), ESD, and other reliability assessments.
- Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical requirements.
- Perform floor planning and detailed signal planning for complex analog circuits, ensuring optimization for area, power, reliability, and performance.
- Drive the development and implementation of innovative analog layout methodologies to improve productivity and layout quality.
- Troubleshoot issues related to design, tools, flows, and methodologies utilized in analog layout design.
- Collaborate closely with cross-disciplinary teams to meet design specifications, align on requirements, and negotiate layout tradeoffs.
Behavioral traits that we are looking for:
- Collaboration: Works effectively in team environments and seeks input from others
- Learning Agility: Demonstrates curiosity and quickly adapts to new tools, technologies, and concepts
- Attention to Detail: Carefully reviews work to ensure accuracy and quality
- Problem Solving: Approaches technical challenges with structured thinking and persistence
- Accountability: Takes ownership of assigned tasks and follows through on deliverables
- Communication: Clearly shares ideas and asks questions when clarification is needed
- Growth Mindset: Open to feedback and continuously improving skills
Why Join Us
- Work on cutting-edge semiconductor technologies
- Learn from experienced engineers and mentors
- Opportunities for career growth and technical development
- Collaborative, inclusive engineering culture
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
- See Intel Benefits for more details.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field of study with 3+ years of experience. Or a Master’s degree in the same field with 2+ years experience.
Your experience described above must be in the following:
- Analog device and metal layout fundamentals, including analog/mixed-signal fundamentals
- Cadence Virtuoso Layout Suite and Calibre/ ICV DRC for design and verification tasks
- CMOS technologies and high-voltage rules
- Floor planning and hierarchical layout planning for analog and mixed-signal blocks
- Conducting performance verification for layouts and debug layout-related issues
Preferred Qualifications and Experience:
- Strong understanding of analog layout effects including mismatch, parasitics, IR drop, electromigration (EM), and coupling, and their impact on circuit performance
- Apply best practices for common-centroid, interdigitation, and symmetry-based layouts to minimize mismatch and variation
- Evaluate and mitigate process variations and gradient effects across sensitive analog blocks
- Ensure robust layout through parasitic-aware design, working closely with extraction (xtract/spef) and simulation teams
- Debug layout-related issues by correlating LVS, DRC, xtract, and silicon behavior
- Optimize layouts for noise isolation, shielding, and signal integrity, especially in mixed-signal environments
Join us in shaping the future of technology. Apply today and be part of a team that's driving innovation at Intel.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 3+ years experience (or Master's with 2+ years).
- Analog device and metal layout fundamentals, including analog/mixed-signal fundamentals.
- Experience with Cadence Virtuoso Layout Suite for layout implementation.
- Experience with Calibre and ICV for DRC and layout verification.
- Knowledge of CMOS technologies and high-voltage rules.
- Floor planning and hierarchical layout planning for analog and mixed-signal blocks.
- Conducting performance verification for layouts and debugging layout-related issues (LVS, DRC correlation).
- Understanding of ESD, IR drop, electromigration, and other reliability assessments.
- Experience with parasitic extraction and formats/tools such as xtract and SPEF and working with extraction/simulation teams.
- Apply best practices for common-centroid, interdigitation, symmetry, noise isolation, shielding, and signal integrity in mixed-signal layouts.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
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