Analog Circuit Design Engineer

Posted 8 Hours Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Designs and optimizes high-performance analog and mixed-signal circuits for SerDes, memory interfaces, and advanced process nodes. Responsibilities include circuit simulation, parameter extraction, test planning, post-layout validation, post-silicon debugging, and optimization for power, area, timing, yield, and reliability. The role collaborates with architecture and layout teams, improves design methodologies, and uses industry-standard EDA tools.
Summary Generated by Built In
Job Details:

Job Description: 

The Role and Impact:

As an Analog Circuit Design Engineer, you will play a pivotal role in designing advanced analog circuits for cutting-edge technologies. Your day-to-day work will focus on creating high-performance, power-optimized circuits for analog and mixed-signal IPs in advanced process nodes. By collaborating with cross-functional teams, you will shape Intel's ability to deliver robust and innovative solutions that meet global technology demands.
Business Group:

You will join the Central Engineering Group (CEG), a team dedicated to enabling Intel's success through world-class engineering capabilities. CEG is focused on the development of state-of-the-art technologies, contributing to Intel's leadership in innovation and product excellence.
Key Responsibilities:

- Design, develop, and optimize analog circuits for high-speed SerDes, memory interfaces, and advanced process nodes.
- Extract key chip parameters, simulate analog behavior models, and validate designs against block specifications.
- Create and execute comprehensive test plans to ensure functionality, reliability, and performance.
- Collaborate with architecture and layout teams to optimize circuits for power, area, timing, and electrical robustness.
- Perform post-silicon debug to analyze and resolve circuit issues, ensuring readiness for high-volume manufacturing.
- Continuously improve design methodologies to enhance innovation, efficiency, and turnaround times.
- Utilize industry-standard tools such as Cadence Virtuoso, SPICE simulators, and post-layout extraction tools.

Qualifications:

Minimum Qualifications:

- Bachelor's degree in Electrical Engineering or a related field with 6+ years of experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience in analog circuit design.
- Proficiency in designing high-speed analog/mixed-signal circuits, including PLLs, SerDes, regulators, and clocking circuits.
- Expertise in CMOS design fundamentals, circuit simulation tools, and modeling.
- Experience with EDA tools such as Cadence Virtuoso, Spectre, PrimeSim, DRC, LVS, and post-layout extraction.
- Familiarity with optimizing circuits for power efficiency, area, and yield goals.
Preferred Qualifications:

- Experience in post-silicon validation, reliability testing, and debugging.
- Knowledge of scripting languages such as Python, TCL, or Perl for design automation tasks.
- Familiarity with high-speed interface interconnect modeling and simulation.
- Strong analytical and problem-solving skills, along with a demonstrated ability to lead technical initiatives.
- Proven ability to work in fast-paced environments and mentor junior engineers.
If you are excited about driving innovation and crafting impactful analog designs, we encourage you to apply and contribute to transforming technology at Intel.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor’s degree in Electrical Engineering or a related field with 6+ years of analog circuit design experience
  • Master’s degree in Electrical Engineering or a related field with 4+ years of analog circuit design experience
  • PhD in Electrical Engineering or a related field with 2+ years of analog circuit design experience
  • Experience designing high-speed analog and mixed-signal circuits, including PLLs, SerDes, regulators, and clocking circuits
  • Expertise in CMOS design fundamentals, circuit simulation tools, and modeling
  • Experience with Cadence Virtuoso, Spectre, PrimeSim, DRC, LVS, and post-layout extraction
  • Experience optimizing circuits for power efficiency, area, and yield goals
  • Experience in post-silicon validation, reliability testing, and debugging
  • Knowledge of Python, TCL, or Perl for design automation
  • Familiarity with high-speed interface interconnect modeling and simulation
  • Strong analytical and problem-solving skills with demonstrated ability to lead technical initiatives
  • Ability to work in fast-paced environments and mentor junior engineers

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
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Year Founded: 1968

What We Do

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