Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.
The ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.
Key Responsibilities-
• Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.
• Develop and drive architecture and circuit implementation for:
• High-speed TX and RX circuits
• Serializer/Deserializer (SerDes) building blocks
• PLLs, DLLs, CDRs, and clocking circuits
• Equalization and signal conditioning circuits
• Bandgap references, bias generation, and LDOs
• ESD protection and IO pad circuitry
• Perform detailed transistor-level design, simulation, and verification across multiple PVT corners.
• Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.
• Collaborate closely with physical design teams on layout reviews and post-lay out optimization.
• Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.
• Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.
• Mentor junior engineers and contribute to team-wide design methodologies and best practices.
• Drive technical reviews and provide leadership in solving complex design challenges.
Bachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.
• 5 to 9 years of industry experience in analog/mixed-signal IC design.
• Strong expertise in CMOS analog circuit design fundamentals.
• Proven experience designing high-speed analog circuits in advanced technology nodes.
• Hands-on experience with one or more of the following: SerDes architectures, High-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, Clock distribution networks, Reference and bias circuits, LDOs and power management circuits.
• Deep understanding of circuit noise, mismatch, jitter, stability, and reliability considerations.
• Strong experience with Cadence Virtuoso, Spectre, and industry-standard analog verification flows.
• Expertise in: Corner analysis, Monte Carlo simulations, Statistical design methodologies, post-layout verification and extraction analysis, Strong debugging and analytical problem-solving skills.
• Experience with industry-standard high-speed interfaces such as: PCI Express (PCIe), DDR Memory Interfaces, USB, Ethernet, MIPI, DP, eDP, HDMI, UCIe.
• Experience in advanced process technologies such as FinFET and Gate-All- Around (GAA) nodes.
• Knowledge of signal integrity, channel modelling, and equalization techniques.
• Experience in silicon validation and lab characterization.
• Familiarity with reliability signoff, ESD verification, and EM/IR analysis.
• Scripting experience using Python, Perl, TCL, or SKILL for design automation and productivity enhancement.
Key Competencies
• Technical leadership in analog and mixed-signal design.
• Strong communication and stakeholder management skills.
• Ability to work effectively in global, cross-functional environments.
• Structured problem-solving and decision-making capabilities.
• Passion for innovation and continuous improvement.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's or master's degree in electrical engineering, electronics engineering, VLSI, microelectronics, or a related discipline
- 5 to 9 years of industry experience in analog or mixed-signal IC design
- Strong expertise in CMOS analog circuit design fundamentals
- Experience designing high-speed analog circuits in advanced technology nodes
- Experience with SerDes architectures, high-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, clock distribution networks, reference and bias circuits, LDOs, or power management circuits
- Understanding of circuit noise, mismatch, jitter, stability, and reliability considerations
- Experience with Cadence Virtuoso, Spectre, and analog verification flows
- Experience with corner analysis, Monte Carlo simulations, statistical design methodologies, post-layout verification, and extraction analysis
- Strong debugging and analytical problem-solving skills
- Experience with high-speed interfaces such as PCIe, DDR, USB, Ethernet, MIPI, DP, eDP, HDMI, or UCIe
- Experience with advanced process technologies such as FinFET and Gate-All-Around nodes
- Knowledge of signal integrity, channel modeling, and equalization techniques
- Experience in silicon validation and lab characterization
- Familiarity with reliability signoff, ESD verification, and EM/IR analysis
- Scripting experience using Python, Perl, Tcl, or SKILL
- Technical leadership, communication, stakeholder management, and cross-functional collaboration skills
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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