Jobs at Tenstorrent Inc.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

As a Staff Machine Learning Engineer, you will optimize AI models for custom devices, experiment with state-of-the-art architectures, and collaborate to solve complex problems in real-world applications.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Develop and optimize the ML training framework in high-performance C++, implement new ops and layers, debug and tune model performance on Tenstorrent chips, collaborate with compiler and kernel teams, and support integration and productionization of real-world models.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Build and run an enterprise sales motion for AI hardware and software: own accounts through the full lifecycle, align technical solutions to business value, collaborate cross-functionally, develop repeatable processes and materials, and manage long, complex procurement cycles to accelerate revenue.

Lead manufacturing cost accounting including inventory, fixed assets, and COGS. Build and scale standard costing, cost roll-ups, and controls for IPO readiness. Analyze manufacturing variances, partner with Supply Chain, Sales, and R&D, and deliver COGS and margin reporting to leadership.

Lead and scale global IT: own enterprise systems, infrastructure, security partnerships, end-user experience, and IT operations. Drive strategy, roadmaps for business applications, integrations, automation, and internal service delivery while partnering with cross-functional leaders to support rapid AI hardware and software growth.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.

Own multi-layer PCB layouts for high-performance AI and computing products. Route high-speed interfaces (GDDR/LPDDR/DDR, PCIe Gen5/6, Ethernet, USB), apply layout rules, select advanced fabrication (HDI, blind/buried vias, back drilling, VIPPO), collaborate with power, SI, and mechanical teams, and resolve DFM/DFA/DFT feedback to meet manufacturability and regulatory standards.

Design, deploy, and operate global data center networks for AI compute clusters. Manage switches, routers, firewalls, and lossless RDMA fabrics, troubleshoot production incidents, collaborate with hardware and platform teams, and build automation for scalable, secure, high-performance network provisioning and operations.

Lead the development of AI compiler tools, enhance performance analysis, collaborate with hardware teams, and mentor engineers to improve compiler tooling.

Develop and maintain infrastructure platforms for AI services, build APIs, manage Kubernetes clusters, and automate workflows using CI/CD practices.

Select and qualify electronic components for high-performance AI compute systems, maintain Approved Vendor List, drive multi-sourcing and cost optimization, monitor lifecycle and supplier risk, and collaborate with hardware, procurement, and supply teams to ensure component availability for scalable production.

Lead and deliver agentic workflow and program intelligence initiatives: define opportunities, structure ambiguous work into programs, integrate systems and data pipelines, drive automation, partner with engineering, infrastructure, and data teams, and produce executive-ready reporting.

The Risc-V Architect will analyze AI workloads, design custom RISC-V cores, and lead the architecture efforts at Tenstorrent, improving CPU performance.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.