Jobs at Tenstorrent Inc.

The role involves full-custom layout of mixed-signal ICs, focusing on performance and integration into SoCs using advanced FinFET processes.

Lead the System IP development and manage the India engineering site, ensuring the execution of technical roadmaps and operational success.

As a Senior Engineer in System-Level Design Verification, you will validate AI silicon's performance, ensuring system connectivity and functionality across large compute platforms, while collaborating with hardware and software teams to achieve silicon targets.

Design and architect chiplets for automotive SoC, focusing on performance and safety requirements while collaborating across engineering teams.

As Director of Customer Engineering, manage technical customer relationships, translate needs into engineering specifications, and enhance collaboration between customer teams and internal engineering.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Develop and enhance verification infrastructure for RISC-V CPU clusters, working on complex hardware subsystems and multi-IP interactions.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

Lead chiplet and chip-top physical implementation for high-performance CPU SoCs in a system-in-package environment, driving design closure and mentor junior engineers.

The role involves driving power analysis and optimization for CPU chiplet designs, including managing power projections, collaborating with multiple teams, and evaluating new optimization techniques.

As a Staff Digital Design Engineer, you will optimize SoC architectures focusing on performance and power-aware design, collaborating with various teams on cutting-edge chiplet design.

The role involves CPU core verification for out-of-order RISC-V CPUs, requiring in-depth microarchitecture knowledge and development/debugging of functional verification models.

The PCB Layout Engineer will design multi-layer PCB layouts for high-performance computing and AI hardware, ensuring specifications for mass production. Responsibilities include routing high-speed interfaces and collaborating with cross-functional teams to meet design requirements.

Drive top-level implementation of complex AI and CPU SoC designs, ensuring design closure and optimizing chip-level implementations for power, performance, and area.

The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

Support and maintain Linux infrastructure for EDA and silicon design. Manage schedulers, install/debug EDA tools, and monitor system health.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.