Jobs at Tenstorrent Inc.

Build and maintain reliable infrastructure for silicon-development workloads, including simulations, verification, formal analysis, EDA, CI/CD, and repository health. Optimize performance and throughput, reduce engineering wait times, create monitored services with automated recovery, and develop AI-agent workflows for testing and debugging. Partner with hardware and software teams to resolve recurring integration failures and improve developer productivity.

Drive complex, cross-functional platform engineering initiatives across runtime systems, device drivers, deployment, observability, hardware, and architecture teams. Develop technical execution plans, manage dependencies, improve reliability and scalability, establish milestones and metrics, investigate risks, and unblock engineering progress. The role supports hardware/software integration, fleet-scale deployment, debugging, platform readiness, and engineering workflow improvements through telemetry, dashboards, automation, and AI-assisted tools.

Develop and support compiler, runtime, and model-integration workflows for Tenstorrent AI IP. Work directly with customers to bring computer vision and large language models into Tenstorrent platforms, investigate compatibility issues, validate integrations, and solve technical challenges across software, compiler, hardware, and IP layers.

Define and implement low-level runtime software for custom processors, accelerators, memory systems, and data-movement IP. Responsibilities include hardware initialization, workload dispatch, scheduling, synchronization, resource management, performance optimization, system bring-up, and debugging. The role collaborates across hardware, firmware, compiler, and systems teams, influences runtime architecture, supports customers, and mentors engineers while improving latency, throughput, scalability, and reliability.

Develop and optimize automated test equipment programs for AI and compute silicon using the Advantest V93000. Responsibilities include creating modular test and measurement libraries, implementing parametric, functional, scan, BIST, and system-level tests, debugging failures, supporting silicon characterization, extracting Vmin/Fmax, defining production limits, and improving datalogging, yield analysis, test time, multisite efficiency, and measurement stability for NPI and high-volume manufacturing.

Optimize software workloads across datacenter and agentic AI applications on RISC-V platforms. Responsibilities include profiling applications and runtimes, identifying bottlenecks, tuning compilers and runtimes, analyzing memory and concurrency behavior, leveraging vector, matrix, and custom ISA capabilities, and developing AI-assisted optimization workflows. The role collaborates across software, compiler, hardware, and performance modeling teams to improve throughput, latency, efficiency, and future CPU architecture.

Design and implement low-level kernels and software primitives for Tenstorrent AI hardware. Optimize performance through profiling, bottleneck analysis, implementation, and validation. Develop software supporting model bring-up and execution, collaborate with hardware, runtime, tools, and architecture teams, and improve the quality and capabilities of the low-level software stack.

Own customer program coordination for accelerated compute IP products, aligning product milestones, deliverables, customer engagement plans, and statements of work. Coordinate architecture, engineering, software, product, and sales stakeholders; maintain program plans, tracking processes, service-level agreements, and escalation paths. Lead program reviews, communicate risks and status to executives, drive corrective actions, and improve processes using AI tools.

Develop and apply formal verification techniques to validate high-performance RISC-V CPUs and AI compute platforms. Build properties, assertions, assumptions, constraints, coverage analyses, and formal verification environments; analyze counterexamples and debug RTL failures. Collaborate with CPU architects, RTL designers, and design verification engineers to verify complex microarchitectural behavior and resolve issues. The role requires strong SystemVerilog and SVA skills, digital design and computer architecture knowledge, and programming or scripting experience in Python, Tcl, C, or C++.

Partners with North American senior leaders on organizational design, leveling, performance calibration, investigations, reorganizations, sensitive employee matters, and exits. Diagnoses underlying organizational and people issues, guides difficult leadership decisions, and ensures fair promotion and performance practices. The role independently owns HR challenges from start to finish while helping build scalable People function systems during rapid growth.

Own commercial contracting and related legal functions across the contract lifecycle, including drafting, negotiation, execution, and post-execution management. Advise teams on data privacy, cybersecurity, compliance, supply chain, manufacturing, and business matters. Develop templates, playbooks, fallback positions, policies, and CLM workflows while partnering with leadership, engineering, product, sales, finance, security, IT, and operations.

Analyze datacenter and agentic AI workloads on next-generation RISC-V CPUs. Characterize workload behavior, identify performance bottlenecks using profiling and simulation, reduce production workloads for modeling, correlate simulations with hardware, and recommend architectural improvements. Collaborate with CPU architects, RTL designers, compiler teams, and software engineers across hardware/software boundaries to improve CPU performance, scalability, throughput, and efficiency.

Develop and scale system-level test frameworks for AI silicon in high-volume manufacturing. Build test wrappers, harnesses, abstraction layers, telemetry, logging, failure signatures, and automated triage. Integrate functional, stress, and diagnostic tests while debugging issues across hardware, firmware, drivers, operating systems, and test equipment. Collaborate with validation, manufacturing, product engineering, and silicon teams to establish reliable execution, pass/fail criteria, and data standards for yield and RMA analysis.

Lead global strategic sourcing and supplier management for DRAM and NAND storage products. Own commodity strategy, negotiations, capacity commitments, supplier performance, supply continuity, inventory exposure, and risk mitigation from product introduction through volume production. Partner with engineering, operations, finance, procurement, and contract manufacturers to align forecasts, technology roadmaps, qualification, costs, and production readiness.

Own customer-facing AI system outcomes from integration through production operations. Responsibilities include hardware and software integration, deployment, validation, automation, debugging, production coding, observability, release engineering, and operational procedures. Work directly with customer engineering teams on Kubernetes- and Linux-based multi-node AI or HPC environments, including LLM inference deployments. Requires strong Python engineering, systems expertise, and native or business-level Japanese plus business-level English.

Lead complex chiplet-based SoC development programs from architecture through tape-out. Coordinate design, verification, physical design, DFT, software teams, and external contributors; maintain program plans, milestones, deliverables, reviews, dependencies, and risk mitigation. The role supports RISC-V CPU servers, machine learning processors, memory, and I/O functionality while driving cross-functional execution and stakeholder communication.

Senior in-house counsel will manage commercial contracts end to end, advise on data privacy, cybersecurity, compliance, supply chain, and manufacturing matters, and support cross-functional teams. The role involves negotiating technology, SaaS, hardware, vendor, licensing, and manufacturing agreements; developing templates, playbooks, fallback positions, and CLM workflows; and serving as a practical legal advisor in a fast-paced semiconductor and AI technology environment.

Designs full-custom analog and mixed-signal IC layouts for high-speed blocks and SoC integration. Responsibilities include floorplanning, placement, routing, parasitic optimization, matching, EM/IR, ESD, latch-up, and physical verification closure across advanced FinFET nodes. The engineer supports extraction and simulation and may develop automation scripts and layout methodologies. This is a remote U.S.-based role requiring collaboration with circuit designers and delivery of manufacturable silicon.

Provides onsite IT and data center administration for Toronto operations. Responsibilities include racking, cabling, deploying, maintaining, relocating, and decommissioning servers, networking equipment, and storage systems; supporting migrations and disaster recovery; managing inventories; handling onboarding, device setup, desk-side support, and troubleshooting; documenting procedures; tracking tickets; and coordinating with engineering teams, vendors, and data center personnel.

Own end-to-end design verification for IOMMU and system IP, including specification review, test planning, constrained-random verification, coverage analysis, regression debugging, and sign-off. Build scalable SystemVerilog/UVM environments, verify standard bus protocols, automate workflows with scripting, and collaborate with architecture, RTL, and validation teams. The role is hybrid in Bangalore and involves CPU and memory-management IP for AI/ML systems.