Jobs at Tenstorrent Inc.

The Business Development Lead will identify opportunities, manage client relationships, and support go-to-market execution for AI solutions in India.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

As a Senior Software Engineer at Tenstorrent, you will develop AI compiler technologies, optimize computational graphs, and enhance MLIR frameworks to connect AI models with hardware.

Lead customer engagements for RISC-V CPU server and machine learning processor projects, coordinating with engineering teams and managing technical program requirements.

The SoC Physical Design Verification Engineer leads full-chip signoff, ensuring high-quality silicon through physical verification and debugging across teams for successful tapeouts.

Responsible for building quality organization across hardware systems and custom silicon, driving quality standards, audits, and continuous improvement initiatives.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

The role involves designing and optimizing performance-critical kernels for AI hardware, debugging low-level issues, and collaborating with cross-functional teams.

As a Senior Engineer, you will develop cutting-edge AI compiler technologies, optimize computational graphs, and build frameworks for diverse AI models.

As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.

Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, involving hands-on infrastructure development and debugging using AI methodologies.

The role involves defining and implementing RTL for high-performance RISC-V CPUs, collaborating with various teams to ensure design meets functional, timing, and power goals while using innovative optimization techniques.

The Global Supply Chain Manager will oversee supplier management, improve supply chain efficiency, and collaborate across teams to drive cost reductions and mitigate supply risks.

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

Design, implement, and optimize low-level compute kernels for parallel ML workloads. Write high-performance C/C++ code, tune instruction-level latency, memory, and bandwidth, profile and debug a low-level software stack, and collaborate with ML and hardware engineers to integrate optimizations into production ML pipelines.

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

Perform post-silicon power characterization and correlation for AI SoCs: develop and run power measurement strategies in the lab, analyze results vs pre-silicon models, support debug with architecture and validation teams, extend automation and scripts, and produce end-to-end power correlation reports and recommendations.

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

As a Staff Engineer, you will own verification for CPU core features, develop functional models, and collaborate with cross-functional teams to enhance design quality.

The Munich Site Manager will lead program planning and execution for silicon and platform initiatives, enhancing collaboration and driving technical direction in Munich.