Teams at Tenstorrent Inc.

Drive CPU performance verification and RTL-to-performance-model correlation for a high-performance RISC-V CPU. Analyze performance data, identify bottlenecks, develop microbenchmarks and performance tools, debug RTL across pre-silicon environments, and collaborate with architects and RTL engineers to validate performance features and optimize power, performance, and area.

Contribute to physical design of high-performance AI/ML chips from synthesis through tapeout. Responsibilities include floorplanning, clocking, I/O planning, timing closure, power and area optimization, and signoff. The role requires collaboration across ASIC disciplines and expertise with physical design flows, timing, EM/IR, and power analysis. Engineers will develop automation skills and end-to-end ASIC implementation knowledge while optimizing advanced semiconductor designs.

Implement and integrate DFT features including scan, JTAG, compression, ASST, and MBIST across ASIC IPs from RTL through tapeout. Own ATPG, test coverage analysis, gate-level simulation, and MBIST verification while developing DFx methodologies that integrate with front-end and physical design flows. Collaborate with design, physical design, verification, test, and manufacturing teams to optimize coverage, test cost, debug, yield learning, and silicon bring-up.