Jobs at SK hynix

Design, implement, and integrate Flash Interface Layer firmware for SSDs. Debug on FPGA/ASIC, develop NAND management algorithms and device drivers, and collaborate with SoC, hardware, and validation teams to deliver production-quality embedded firmware.

Design and implement firmware for FTL, SSD products; perform code reviews, debugging, and collaborate for issue resolution.

The intern will develop and validate storage test software, focusing on coding, debugging, and creating technical documentation for tools in semiconductor technology.

Design, deploy, and maintain on-prem AI infrastructure and agentic systems. Build GPU clusters, model serving, vector DB-backed RAG pipelines, fine-tune and deploy models, implement governance (MCP), and automate CI/CD and monitoring to integrate AI capabilities into enterprise workflows.

Lead validation and system-level testing for enterprise PCIe NVMe SSDs. Manage test progress, debug system issues with SOC/FW/HW teams, analyze bugs, use bus analyzers and trace tools, and provide customer-facing technical support to ensure product reliability and compliance.

The test engineer will validate SSD reliability through developing test plans and automation scripts, analyzing results, and collaborating on defect resolution.

Lead leadership and organization development initiatives including compensation benchmarking, HR reporting and analysis, performance and promotion frameworks, organizational restructuring, cross-functional change management, recruiting Bay Area engineers, coordinating executive meetings, and handling expatriate and confidential HR matters.

The Sr. Principal FTL Engineer will design and implement Flash Translation Layer for SSDs, perform firmware evaluations, and conduct debugging and integration.

The Program Manager will oversee enterprise SSD development by coordinating with various teams, managing schedules, and providing project updates while ensuring smooth communication between teams.

The role involves designing and automating test plans for enterprise SSDs and server storage systems while collaborating with development teams to resolve defects and ensure product quality.

Design, develop, and automate test plans for SSD products, ensure product quality, and collaborate with teams for reliable solutions during the development cycle.

Lead the design and execution of test plans for PCIe and NVMe enterprise SSDs, collaborating with teams to ensure product reliability and compliance with specifications.

Design, implement, and debug Flash Translation Layer (FTL) and real-time embedded firmware for SSD products. Perform firmware code reviews, integration, performance profiling, validation, failure analysis, and corrective actions in collaboration with stakeholders. Contribute to system-level debugging and optimization for multi-core ARM-based controllers.

Develop signal integrity and power integrity solutions for SSD products, including design reviews, validations, and mentoring engineers. Requires strong experience with high-speed interfaces and simulation tools.

Design and implement FTL and embedded system firmware for SSD products; perform code review, system integration, validation, and failure analysis.

Develop and execute comprehensive firmware verification plans for SSDs, design automated white/grey/black-box tests in Python, run end-to-end testing across simulation, FPGA, and prototype hardware, analyze regression failures, root-cause firmware bugs, collaborate on code reviews, and own test reporting and issue resolution.

Develop and deploy AI agents and agentic workflows to automate test execution and scheduling. Implement MCP integrations, build Ansible playbooks, maintain test environments and lab equipment, run automation, triage failures, and report results.

The Staff Engineer will design high-speed interfaces for NVME or Chiplet storage subsystems, oversee multi-functional team efforts, and mentor engineers for silicon success.

Design RTL (Verilog/SystemVerilog) for SoC/IP used in high-performance SSD controllers. Collaborate with verification, silicon validation, and firmware teams. Drive micro-architecture, timing closure, and tapeout readiness while documenting designs and ensuring implementation quality.