Jobs at SK hynix

Develops signal and power integrity solutions for next-generation SSDs, including controller package and PCB design. Responsibilities include pre- and post-layout simulation, stack-up and routing definition, design reviews, lab validation, measurement correlation, debugging, root-cause analysis, documentation, cross-functional collaboration, customer escalations, and mentoring engineers. The role focuses on high-speed PCIe, DDR, NAND, and power delivery networks.

Lead advanced-node ASIC physical design from synthesis through GDS and tapeout. Drive placement, CTS, routing, timing closure, extraction, physical verification, and power integrity signoff for high-performance SoCs. Develop automation flows, optimize power, performance, and area, resolve design-rule and reliability issues, collaborate across engineering teams, and mentor junior engineers.

Conduct research on closed-loop AI-assisted hardware/software co-design flows for SoC development. Structure, implement, and evaluate loops involving search, verification, simulation, RTL, and physical design. Apply loops to microarchitecture, RTL implementation, verification, or power-performance-area optimization. Build reliable, reproducible workflows with caching, regression checks, clear interfaces, and reporting, then document findings and recommend design-automation practices.

Conduct research in SoC design automation, AI-assisted hardware/software co-design loops, and AI infrastructure. Build and evaluate automated flows using simulators, software builds, ASIC or FPGA CAD, and AI agents. Measure power, speed, area, correctness, workload performance, search costs, and reproducibility. Study memory-device behavior, system bottlenecks, compute-memory architectures, and their effects on AI quality, latency, throughput, and energy. Own research questions, methods, and written results.

Develops signal and power integrity solutions for next-generation SSD controller packages, substrates, and PCBs. Responsibilities include high-speed interface simulation, PCB stack-up and routing guidance, design reviews, lab validation, simulation-measurement correlation, debugging, root-cause analysis, customer escalations, documentation, and mentoring engineers. The role collaborates with SoC, firmware, package, and circuit design teams to ensure system-level requirements are met.

Lead end-to-end physical design implementation for advanced-node SoC designs from synthesis through GDS and tapeout. Responsibilities include placement, CTS, routing, timing closure, RC extraction, physical verification, IR drop and electromigration analysis, power-grid optimization, and flow automation. The role requires collaboration with cross-functional design teams, development of physical design methodologies, and mentoring junior engineers.

Develops firmware verification plans and automated Python tests for NVMe, enterprise SSD, security protocols, and customer specifications. Performs end-to-end testing across simulations, FPGA prototypes, and SSD hardware; investigates regression failures and resolves complex firmware defects. Collaborates with firmware engineers through code reviews to improve architecture and test coverage. Owns test reporting and communicates technical issues, solutions, and mitigation plans to engineering and management.

Develop and deploy AI agents and agentic workflows to automate test execution and scheduling. Implement MCP integrations, build Ansible playbooks, maintain test environments and lab equipment, run automation, triage failures, and report results.

Designs, deploys, configures, documents, and maintains enterprise WAN, LAN, data-center, campus, wireless, firewall, router, switch, monitoring, and VPN infrastructure. Performs upgrades, incident response, troubleshooting, commissioning, and after-hours support. Leads complex network projects, including relocations and campus designs, while managing documentation, change control, security policies, testing, stakeholder communication, and team mentoring.

Develop and validate embedded software for SoCs used in non-volatile memory devices, supporting concept development through mass production. Write software to exercise SoC components and contribute to storage solution development. The role requires embedded or firmware-level programming in Rust or C/C++, Python scripting and testing, and knowledge of digital circuits, computer architecture, and memory systems.

Designs, implements, debugs, and improves Flash Translation Layer firmware and real-time embedded systems for SSD products. Responsibilities include code reviews, system integration, performance profiling, validation, failure analysis, and corrective firmware actions. The role requires collaboration across teams to resolve issues and expertise in embedded controllers, storage protocols, firmware programming, and debugging tools.

Develop and validate storage test software and tools based on industry specifications and firmware algorithms. Responsibilities include coding and debugging in C++, Python, JavaScript, and related technologies; designing storage test tools and APIs; automating builds, deployments, testing, and performance reporting; validating functionality and scalability; and creating technical documentation. The internship lasts six months, requires 40 hours per week, and is located in San Jose.

Leads leadership and organization development initiatives, including compensation benchmarking, HR reporting, performance and promotion frameworks, organizational restructuring, executive support, change management, and technology recruiting. Provides leadership dashboards and analysis, coordinates executive meetings and events, supports expatriates, and handles confidential information. Requires bilingual English and Korean fluency, extensive progressive HR experience, strong organizational skills, advanced Microsoft Office proficiency, and full-time onsite availability.

Leads HR and organizational development initiatives, including compensation benchmarking, performance and promotion frameworks, restructuring, leadership management, HR reporting, recruiting, change management, executive coordination, and expatriate support. The role requires fluent English and Korean, extensive progressive HR experience, strong discretion, advanced Microsoft Office skills, and full-time onsite availability.

Design, develop, and automate test plans for SSD products, ensure product quality, and collaborate with teams for reliable solutions during the development cycle.

Design and implement SSD flash interface firmware, integrate modules, and debug issues in FPGA and ASIC environments. The intern will work with SoC, hardware, and validation teams while developing NAND management and error-control functionality. Responsibilities include firmware development, debugging, code and design reviews, and producing product-quality output. The role is a six-month, 40-hour-per-week internship in San Jose for students or recent graduates in electrical engineering, computer science, or a related field.

Design, implement, and integrate Flash Interface Layer firmware for SSDs. Debug on FPGA/ASIC, develop NAND management algorithms and device drivers, and collaborate with SoC, hardware, and validation teams to deliver production-quality embedded firmware.

Design and implement firmware for FTL, SSD products; perform code reviews, debugging, and collaborate for issue resolution.

Design, deploy, and maintain on-prem AI infrastructure and agentic systems. Build GPU clusters, model serving, vector DB-backed RAG pipelines, fine-tune and deploy models, implement governance (MCP), and automate CI/CD and monitoring to integrate AI capabilities into enterprise workflows.

The Sr. Principal FTL Engineer will design and implement Flash Translation Layer for SSDs, perform firmware evaluations, and conduct debugging and integration.