Teams at Renesas Electronics

Maintain and govern global master data across SCM/ERP systems, ensuring data quality, governance, and auditability. Perform reviews, cleanups, KPI monitoring, root-cause analysis, support migrations and testing, drive standardization, automation, documentation, and stakeholder training.

Design, develop, and improve digital verification environments and flows. Run RTL and gate‑level simulations and daily regressions. Create tests, assertions, and coverage metrics; analyze and close coverage. Debug designs, work with UVM/SystemVerilog (including UVM internals), and collaborate on verification architecture and automation.

Lead test engineering for gate drivers, power stages, and isolators: define ATE test architecture on Cohu/Acco platforms, design/load board and probe card reviews, solve SI/thermal for high-voltage GaN, drive NPI test builds and DfT discussions, improve yield via statistical analysis, reduce test time and cost, and act as technical focal point for cross-functional teams.