Jobs at Rambus

Develop and maintain secure embedded firmware for Silicon IP products, including drivers, applications, hardware abstraction models, and testing tools. Responsibilities include performance optimization, software refactoring, documentation, code reviews, secure deployment, and cross-functional product architecture. The role requires strong C++ development, Linux, real-time and multithreaded programming, cryptography, security, hardware modeling, and embedded systems expertise.

Designs microarchitecture and RTL for high-performance memory controllers and critical logic blocks. Analyzes performance, power, and area trade-offs; collaborates with verification and physical design teams; debugs regressions; resolves timing and congestion issues; and supports field applications and customer deliveries. Requires extensive ASIC or FPGA logic design experience, strong SystemVerilog/Verilog skills, simulator and scripting experience, and the ability to work independently.

Develops and supports pre-silicon RTL verification for DRAM controller IP using SystemVerilog, UVM, testbenches, functional coverage, regression testing, scripting, and debug. Responsibilities include creating test sequences, monitoring and triaging regressions, correcting verification environments and RTL issues, and supporting controller technologies such as DDR, LPDDR, HBM, and GDDR. The role is intended for a junior engineer or recent college graduate.

Leads semiconductor product programs from concept through mass production, owning schedules, budgets, risks, resources, customer activities, product costs, quality, and program reviews. Partners with engineering and customers to deliver IC products on time and within specification and budget. Presents program status to executives, manages lifecycle exit reviews, coordinates engineering and customer samples, and drives alignment across matrixed teams.

Reviews and processes customer purchase orders, validates commercial terms and billing details, coordinates order issue resolution, and manages order-to-cash activities. Maintains records for compliance, supports backlog and fulfillment reporting, analyzes sales and revenue data, and develops Power BI, Excel, and ERP dashboards. Drives process improvements across forecasting, reporting, and sales operations workflows while collaborating with Sales, Finance, Legal, Operations, and Customer Service.

Lead pre-silicon RTL verification for PCIe and CXL controller IP. Develop UVM testbenches, test sequences, functional coverage plans, regression suites, and verification scripts. Monitor and debug regressions, triage failures, improve test environments, and debug controller RTL designs. Requires strong SystemVerilog, UVM, Verilog, and PCI Express protocol expertise, with Python and Tcl scripting preferred.

Lead pre-silicon RTL verification for memory controller IP supporting DDR, HBM, GDDR, and LPDDR technologies. Develop SystemVerilog testbenches and sequences, plan and implement functional coverage, build and monitor regression suites, debug RTL and verification environments, and develop scripting capabilities using Python and Tcl.

Develop and validate bench and system environments for DDR5 enablement devices, ensuring performance specification compliance. Responsibilities include characterizing I2C/I3C protocols, automating laboratory testing with Python, supporting customers, and providing post-silicon bring-up support while coordinating with design, operations, and development teams.

Architect and develop secure ASIC and silicon IP, including post-quantum cryptography accelerators, random number generators, and cryptographic cores. Responsibilities include researching security techniques, contributing to architecture and design, collaborating with software and security teams, supporting product certification, improving quality and safety, and ensuring compliance with engineering standards. The role requires digital design and front-end ASIC expertise, with knowledge of cryptography, side-channel attacks, back-end flows, DFT, and hardware development in Unix/Linux environments.

Lead microarchitecture and RTL design for high-performance memory controller blocks. Analyze power, performance, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and timing, power, and congestion issues; and support customer pre-sales and post-sales engagements.

Design and verify pre-silicon RTL for PCIe and CXL controller soft IP and PHY integrations. Responsibilities include Verilog RTL design, simulation-based IP integration verification, test-case development, customer integration support, verification-process improvements, requirements traceability, productivity metrics, and progress reporting. The role collaborates with international teams and may require travel abroad.

Own microarchitecture and RTL design for high-performance memory controller blocks. Analyze performance, power, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and resolve timing, power, and congestion issues. Provide technical support for pre-sales customer engagements and post-sales deliveries. The role requires extensive ASIC/FPGA logic design experience and expertise in SystemVerilog or Verilog, simulation tools, and scripting.

Designs microarchitecture and RTL for high-performance memory controller blocks, analyzes performance, power, and area trade-offs, collaborates with verification and physical design teams, debugs regression failures, and supports customer engagements. The role requires extensive ASIC or FPGA logic design expertise, simulator and scripting experience, and offers opportunities to work with advanced memory technologies and interfaces.

Develops pre-silicon RTL verification for memory controller IP supporting DDR, HBM, and GDDR technologies. Responsibilities include testbench and test-sequence development, functional coverage planning, regression testing, debug and triage, RTL issue analysis, and verification-environment scripting. The role requires expertise in SystemVerilog and Verilog, with Python and Tcl scripting preferred, plus substantial design-verification experience.

Designs and implements SystemVerilog and Verilog RTL for DDR5 and DDR6 memory interface products. Responsibilities include block integration, simulation, PPA analysis, timing improvement, functional modeling, design quality checks, verification debugging, documentation, and chip power-on validation. Collaborates with digital, analog, physical design, verification, validation, and product qualification teams.

Leads sourcing strategy for semiconductor foundry and OSAT suppliers, including supplier negotiations, performance monitoring, cost analysis, long-term planning, procurement initiatives, and process improvements. The role manages supply, quality, technology, and cost objectives; supports budgeting and cash-flow activities; drives supplier performance and savings programs; and serves as a procurement consultant for internal and external partners.

Designs, verifies, integrates, tests, and supports memory controller silicon IP. Responsibilities include preparing IP deliveries, integrating third-party IP, debugging simulation failures, developing new RTL functionality, and providing customer support.

Architects high-performance PCIe controller silicon IP for data center and AI applications. Owns architecture specifications, drives technical reviews, collaborates with design, verification, physical design, product, marketing, field, and customer teams, represents the company at PCI-SIG, supports technical presales and customer solutions, develops patents and publications, and trains field teams.

Develop and execute semiconductor test plans across product development, prototypes, high-volume manufacturing, and sustaining support. Design ATE hardware, improve test coverage and yield, optimize test time and multisite performance, debug test patterns, tune timing and levels, and collaborate with design teams, customers, suppliers, and OSAT partners. The role focuses on Advantest V93k-based testing of integrated circuits, preferably including DDR and high-speed digital products.

Lead verification for high-speed DDR memory interface chips from requirements through sign-off. Develop test plans, tests, and UVM-based verification infrastructure for complex blocks, IP, and subsystems. Build testbench architectures, debug issues, guide team members, collaborate with architects, designers, and post-silicon validation teams, and support validation after tapeout.