Jobs at Rambus

Supports Workday HRIS data administration, business processes, audits, payroll and downstream deliverables, reporting, configuration, testing, user support, documentation, training, and process improvement. Maintains accurate and confidential employee data while assisting HR partners, managers, and employees. The role is part-time and hybrid, with regular onsite work in San Jose.

Supports international customers using Rambus DDR4 and DDR5 memory interface chips. Responsibilities include debugging server memory, DRAM, DIMM, BIOS, and signal integrity issues; qualifying and validating new chip designs; conducting failure analysis and 8D reporting; using laboratory equipment and scripting for analysis and automation; preparing technical documentation; and communicating with customers, engineering, marketing, and management. Requires electrical engineering expertise, server platform knowledge, English and Korean communication skills, and international travel.

Lead PMIC lab bring-up, validation, characterization, and post-silicon support across bench, ATE, and system environments. Ensure compliance with performance specifications, power efficiency, and power integrity requirements. Support customers, resolve technical issues, and collaborate with design and marketing teams to define memory power solutions.

Principal Verification Engineer responsible for creating verification plans, developing SystemVerilog and UVM testbenches, implementing reference models, debugging issues, tracking bugs and coverage, and contributing to verification methodology. The role supports DDR memory interface products, collaborates across multidisciplinary and global teams, drives technical solutions, and mentors junior engineers.

Own verification planning and execution for DDR memory interface products. Develop SystemVerilog and UVM testbenches, constrained-random tests, reference models, and coverage strategies. Debug issues, track bugs, contribute to verification methodologies, collaborate across engineering teams, and mentor junior engineers.

Design and architect next-generation PCIe silicon IP, develop RTL using Verilog/SystemVerilog, collaborate with verification teams, prototype designs on advanced FPGAs, and support existing IP generations. The role requires close collaboration with international engineering teams and contributes to PCIe and potentially CXL-based solutions.

Develop pre-silicon RTL verification for memory controller SoftIP supporting DDR, HBM, GDDR, and LPDDR technologies. Responsibilities include creating SystemVerilog testbenches and sequences, planning and coding functional coverage, developing and monitoring regressions, debugging test environments and RTL, and supporting verification scripting capabilities.

Lead verification of secure ASIC cores, including methodology design, test planning, testbench and infrastructure development, coverage analysis, debug, automation, IP integration, and customer support. Partner with architecture, design, security, cryptography, and system test teams. Lead multi-site teams, represent verification practices to customers and executives, and improve quality, release automation, and verification flows using SystemVerilog, UVM or OVM, industry EDA tools, scripting, and advanced verification techniques.

Lead verification for secure ASIC cores, designing test plans, testbenches, verification methodologies, automation, coverage analysis, and debug processes. Collaborate with architecture, design, security, cryptography, system test, customers, and executive stakeholders. Support IP integration, productization, release automation, customer issue resolution, and multi-site team leadership across all hardware project phases.

Develops SI/PI methodologies, package designs, channel simulations, jitter analyses, and decoupling requirements for DDR memory interface products. Partners with chip layout, package, validation, customers, and lab teams to optimize signal performance, correlate simulations with measurements, and support debugging and product bring-up. Requires deep expertise in high-speed memory or SerDes interfaces, electromagnetic and transmission-line theory, equalization, package and PCB design, and commercial EDA simulation tools.

Leads financial planning and analysis for the Memory Interface Chips business unit. Responsibilities include annual budgeting, forecasting, P&L reporting, revenue forecasting, variance analysis, revenue recognition guidance, financial modeling, strategic analysis, and new product introduction metrics. Partners with executives and cross-functional teams, supports earnings and investor communications, and develops finance capabilities and planning systems.

Leads signal and power integrity methodology, package design, modeling, simulations, and analysis for high-speed DDR memory products. Defines packaging, PCB routing, decoupling, channel, jitter, and system requirements; guides design teams using simulation and silicon correlation; collaborates with customers; and supports laboratory debug and bring-up. The role requires extensive DDR4/DDR5 or SERDES experience, electromagnetic and transmission-line expertise, EDA tool proficiency, and lab measurement experience.

Leads FP&A activities including monthly forecasting, annual operating plans, long-range planning, consolidated financial modeling, executive and board reporting, and scenario analysis. Partners with Accounting, IT, Sales, Operations, and data teams to improve planning processes, automate reporting, support ERP enhancements, evaluate strategic investments, and provide financial insights to executive leadership.

Lead semiconductor reliability engineering for new product introductions from project kickoff through production, sustaining support, and RMA. Define qualification, characterization, test coverage, and production flows; manage cross-functional teams, schedules, resources, suppliers, and customers. Optimize yield, cost, cycle time, and quality while supporting failure analysis and product lifecycle activities. Apply data analysis and expertise in wafer fabrication, OSAT testing, ATE, and analog, mixed-signal, and power semiconductor devices.

Develop and maintain secure embedded firmware for Silicon IP products, including drivers, applications, hardware abstraction models, and testing tools. Responsibilities include performance optimization, software refactoring, documentation, code reviews, secure deployment, and cross-functional product architecture. The role requires strong C++ development, Linux, real-time and multithreaded programming, cryptography, security, hardware modeling, and embedded systems expertise.

Develops and supports pre-silicon RTL verification for DRAM controller IP using SystemVerilog, UVM, testbenches, functional coverage, regression testing, scripting, and debug. Responsibilities include creating test sequences, monitoring and triaging regressions, correcting verification environments and RTL issues, and supporting controller technologies such as DDR, LPDDR, HBM, and GDDR. The role is intended for a junior engineer or recent college graduate.

Leads semiconductor product programs from concept through mass production, owning schedules, budgets, risks, resources, customer activities, product costs, quality, and program reviews. Partners with engineering and customers to deliver IC products on time and within specification and budget. Presents program status to executives, manages lifecycle exit reviews, coordinates engineering and customer samples, and drives alignment across matrixed teams.

Reviews and processes customer purchase orders, validates commercial terms and billing details, coordinates order issue resolution, and manages order-to-cash activities. Maintains records for compliance, supports backlog and fulfillment reporting, analyzes sales and revenue data, and develops Power BI, Excel, and ERP dashboards. Drives process improvements across forecasting, reporting, and sales operations workflows while collaborating with Sales, Finance, Legal, Operations, and Customer Service.

Lead pre-silicon RTL verification for PCIe and CXL controller IP. Develop UVM testbenches, test sequences, functional coverage plans, regression suites, and verification scripts. Monitor and debug regressions, triage failures, improve test environments, and debug controller RTL designs. Requires strong SystemVerilog, UVM, Verilog, and PCI Express protocol expertise, with Python and Tcl scripting preferred.

Lead pre-silicon RTL verification for memory controller IP supporting DDR, HBM, GDDR, and LPDDR technologies. Develop SystemVerilog testbenches and sequences, plan and implement functional coverage, build and monitor regression suites, debug RTL and verification environments, and develop scripting capabilities using Python and Tcl.