Jobs at Rambus

Lead manufacturing quality assurance across semiconductor manufacturing partners. Improve process controls, monitor PFMEA and control plans, coordinate 8D investigations and corrective actions, standardize backend packing and labeling requirements, ensure compliance with JEDEC, EIA, and customer standards, and support nonconforming product risk assessments and supplier PCN reviews.

Develop and validate bench and system environments for DDR5 enablement devices, ensuring performance specification compliance. Responsibilities include characterizing I2C/I3C protocols, automating laboratory testing with Python, supporting customers, and providing post-silicon bring-up support while coordinating with design, operations, and development teams.

Leads the architecture, RTL design, integration, validation, debugging, and delivery of complex memory controller silicon IP. Collaborates with architecture, verification, implementation, product, customer, and field teams; defines microarchitecture and design tradeoffs; supports customer integration; and mentors engineers while ensuring high-quality production releases.

Leads end-to-end global semiconductor operations, including foundry and OSAT management, materials strategy, planning, logistics, NPI and production ramp, supply continuity, risk mitigation, cost reduction, and productivity improvement. Builds resilient operations organizations, establishes governance and business continuity plans, manages supplier relationships, and partners cross-functionally to optimize delivery, revenue, margin, and operational performance.

Architect and develop secure ASIC and silicon IP, including post-quantum cryptography accelerators, random number generators, and cryptographic cores. Responsibilities include researching security techniques, contributing to architecture and design, collaborating with software and security teams, supporting product certification, improving quality and safety, and ensuring compliance with engineering standards. The role requires digital design and front-end ASIC expertise, with knowledge of cryptography, side-channel attacks, back-end flows, DFT, and hardware development in Unix/Linux environments.

Lead microarchitecture and RTL design for high-performance memory controller blocks. Analyze power, performance, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and timing, power, and congestion issues; and support customer pre-sales and post-sales engagements.

Design and verify pre-silicon RTL for PCIe and CXL controller soft IP and PHY integrations. Responsibilities include Verilog RTL design, simulation-based IP integration verification, test-case development, customer integration support, verification-process improvements, requirements traceability, productivity metrics, and progress reporting. The role collaborates with international teams and may require travel abroad.

Own microarchitecture and RTL design for high-performance memory controller blocks. Analyze performance, power, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and resolve timing, power, and congestion issues. Provide technical support for pre-sales customer engagements and post-sales deliveries. The role requires extensive ASIC/FPGA logic design experience and expertise in SystemVerilog or Verilog, simulation tools, and scripting.

Designs microarchitecture and RTL for high-performance memory controller blocks, analyzes performance, power, and area trade-offs, collaborates with verification and physical design teams, debugs regression failures, and supports customer engagements. The role requires extensive ASIC or FPGA logic design expertise, simulator and scripting experience, and offers opportunities to work with advanced memory technologies and interfaces.

Leads pre-silicon RTL verification for PCIe and CXL controller IP. Develops UVM/SystemVerilog testbenches and sequences, plans and implements functional coverage, augments regression suites, monitors and debugs regressions, triages RTL and test-environment issues, and develops verification scripting capabilities.

Develops pre-silicon RTL verification for memory controller IP supporting DDR, HBM, and GDDR technologies. Responsibilities include testbench and test-sequence development, functional coverage planning, regression testing, debug and triage, RTL issue analysis, and verification-environment scripting. The role requires expertise in SystemVerilog and Verilog, with Python and Tcl scripting preferred, plus substantial design-verification experience.

Designs and implements SystemVerilog and Verilog RTL for DDR5 and DDR6 memory interface products. Responsibilities include block integration, simulation, PPA analysis, timing improvement, functional modeling, design quality checks, verification debugging, documentation, and chip power-on validation. Collaborates with digital, analog, physical design, verification, validation, and product qualification teams.

Leads sourcing strategy for semiconductor foundry and OSAT suppliers, including supplier negotiations, performance monitoring, cost analysis, long-term planning, procurement initiatives, and process improvements. The role manages supply, quality, technology, and cost objectives; supports budgeting and cash-flow activities; drives supplier performance and savings programs; and serves as a procurement consultant for internal and external partners.

Designs, verifies, integrates, tests, and supports memory controller silicon IP. Responsibilities include preparing IP deliveries, integrating third-party IP, debugging simulation failures, developing new RTL functionality, and providing customer support.

Architects high-performance PCIe controller silicon IP for data center and AI applications. Owns architecture specifications, drives technical reviews, collaborates with design, verification, physical design, product, marketing, field, and customer teams, represents the company at PCI-SIG, supports technical presales and customer solutions, develops patents and publications, and trains field teams.

Develop and execute semiconductor test plans across product development, prototypes, high-volume manufacturing, and sustaining support. Design ATE hardware, improve test coverage and yield, optimize test time and multisite performance, debug test patterns, tune timing and levels, and collaborate with design teams, customers, suppliers, and OSAT partners. The role focuses on Advantest V93k-based testing of integrated circuits, preferably including DDR and high-speed digital products.

Lead verification for high-speed DDR memory interface chips from requirements through sign-off. Develop test plans, tests, and UVM-based verification infrastructure for complex blocks, IP, and subsystems. Build testbench architectures, debug issues, guide team members, collaborate with architects, designers, and post-silicon validation teams, and support validation after tapeout.

Develop test plans and coverage for semiconductor products, design ATE hardware for new product introduction, and support products through prototyping, high-volume manufacturing, and sustaining operations. Optimize yield, test time, and multisite testing while collaborating with design teams, customers, suppliers, and offshore OSAT partners. The role requires expertise with Advantest V93k and familiarity with DFT methodologies, Smartest, Red Hat, and version-control tools.

Leads signal and power integrity modeling, simulation, package design, and system-level analysis for high-speed DDR memory products. Defines packaging, PCB routing, decoupling, channel, jitter, and SI/PI requirements; correlates simulations with laboratory measurements; supports debugging and product bring-up; collaborates with design, validation, customers, and cross-functional teams to optimize performance.

Own chip-level layout collaterals and design assigned blocks using Cadence Virtuoso XL/VXL. Perform Calibre LVS, DRC, antenna, and density verification; resolve reliability issues including EMIR and ESD/latchup. Collaborate with analog designers globally on matching, parasitics, noise isolation, shielding, wells, substrates, and layout-dependent effects. The role requires semiconductor device physics knowledge, advanced-node layout experience, and familiarity with scripting.