Teams at Rambus

Principal Verification Engineer responsible for creating verification plans, developing SystemVerilog and UVM testbenches, implementing reference models, debugging issues, tracking bugs and coverage, and contributing to verification methodology. The role supports DDR memory interface products, collaborates across multidisciplinary and global teams, drives technical solutions, and mentors junior engineers.

Own verification planning and execution for DDR memory interface products. Develop SystemVerilog and UVM testbenches, constrained-random tests, reference models, and coverage strategies. Debug issues, track bugs, contribute to verification methodologies, collaborate across engineering teams, and mentor junior engineers.

Design and architect next-generation PCIe silicon IP, develop RTL using Verilog/SystemVerilog, collaborate with verification teams, prototype designs on advanced FPGAs, and support existing IP generations. The role requires close collaboration with international engineering teams and contributes to PCIe and potentially CXL-based solutions.