Jobs at Quadric

Own customer technical evaluations through design wins by porting and optimizing workloads on Quadric’s Chimera GPNPU. Responsibilities include profiling performance, writing custom kernels, supporting quantization and compiler tooling, debugging with customer engineering teams, and guiding model architecture tradeoffs. The role also develops reusable SDK skills, porting playbooks, benchmark applications, and agentic FDE workflows while relaying customer feedback to engineering and product teams.

Support SoC subsystem development, third-party IP integration, and power, performance, and area optimization for Quadric’s edge AI processor. Assist with low-power digital design, timing closure, architecture documentation, debugging, and front-end RTL development using SystemVerilog or Verilog while collaborating with SoC architects and hardware designers.

Own customer evaluations through design wins by porting and optimizing workloads on Quadric’s Chimera GPNPU. Develop custom kernels, profile performance, debug customer implementations, and guide model architecture tradeoffs. Build reusable SDK skills, porting playbooks, benchmark applications, and agentic FDE tooling. Collaborate with engineering and product teams to incorporate customer feedback into the roadmap.

Develop and extend neural network compiler passes targeting Quadric's GPNPU. Debug compilation issues by tracing generated C++ through compiler pipelines, optimize memory movement and hardware utilization, and contribute to IR transformations, code generation, testing, and developer tools. Collaborate with kernel, hardware, and data science teams while gaining hands-on experience in ML compilation and accelerator-aware optimization.

Define processor microarchitecture, implement RTL in SystemC or SystemVerilog, optimize power, performance, and area, and support timing closure through tapeout. The role owns major design blocks, debugs across the hardware/software stack, packages designs for customer releases, and incorporates customer feedback. Candidates need at least five years of CPU, GPU, or ASIC front-end design experience, strong computer architecture knowledge, digital low-power design expertise, and proficiency with relevant simulation and co-simulation tools.

Develop and optimize AI/LLM kernels and operators for Quadric’s edge AI platform. Profile performance, identify hardware and software bottlenecks, optimize C/C++ code, and contribute to compiler, runtime, and toolchain improvements. The intern will collaborate with senior engineers and gain hands-on experience with hardware-aware inference optimization and GPNPU architecture.

Lead Quadric’s marketing function from the ground up, defining strategy, brand narrative, product marketing, demand generation, PR, developer marketing, and events. Build and manage the marketing team, agencies, processes, budget, and analytics. Partner with product, engineering, business development, and executives on go-to-market initiatives, launches, positioning, sales enablement, communications, analyst relations, and industry presence.

Integrate Quadric’s GPNPU as a backend for llama.cpp, PyTorch, vLLM, and Optimum. Implement memory management, dispatch, operators, model pipelines, serving features, quantization, and performance optimizations. Validate accuracy against reference backends and collaborate with kernel, runtime, and compiler teams to bring up models and production features such as paged KV caching.

Design and integrate SoC subsystems and third-party IP, define architecture, optimize power, performance, and area, contribute to timing closure, debug across hardware and software, and package customer design releases. The role requires hands-on ASIC/SoC front-end experience, SystemVerilog or Verilog expertise, computer architecture knowledge, low-power digital design skills, and subsystem experience in memory, I/O, or compute.

Deploys and optimizes AI models on Quadric’s GPNPU for vision, LLM, VLM, and VLA workloads. Responsibilities include profiling performance, writing and tuning kernels, selecting quantization strategies, debugging accuracy, optimizing compute graphs, and developing automated model deployment, tracing, visualization, pruning, sparsification, and quantization tools.

Develop foundational systems software for Quadric’s General-Purpose Neural Processing Unit, including instruction set simulators, loaders, assemblers, remote debugger infrastructure, drivers, and C++ host and device APIs. Collaborate with hardware and software teams on architecture decisions, performance optimization, binary execution, memory management, abstraction layers, and low-level toolchain development.

Develop and optimize Quadric’s LLVM compiler for its edge AI processor. Responsibilities include implementing support for processor architecture features, building custom front-end and back-end LLVM passes, optimizing code generation, collaborating with hardware engineers on compiler and architecture co-design, and supporting internal and external customers.

Own the full semiconductor IP licensing cycle across North America, from prospecting and technical evaluation through negotiation, closing, and account expansion. Build relationships with SoC and system companies, manage complex multi-stakeholder sales cycles, coordinate benchmarks with field engineers, negotiate license and royalty terms, maintain Salesforce forecasts, and achieve bookings targets. The role requires deep semiconductor IP expertise, technical fluency in NPU and SoC architecture, established industry relationships, and travel of approximately 30%.

Design and integrate SoC subsystems, third-party IP, and processor architecture while optimizing power, performance, and area. Drive timing closure, low-power design, customer-ready releases, and cross-stack hardware/software debugging through tapeout.

Design and optimize deep learning compiler infrastructure for Quadric’s proprietary edge AI processor. Develop MLIR, TVM, and LLVM optimization passes; lower PyTorch, TensorFlow, and ONNX models; implement graph transformations, operator fusion, quantization, memory allocation, and code generation. Benchmark performance and collaborate with hardware teams on instruction extensions, simulators, FPGA bring-up, and ASIC validation. The role requires strong C++ and Python expertise, compiler experience, and knowledge of computer architecture and neural network workloads.

Design and integrate processor-based SoC subsystems, including third-party IP such as NoC, PCIe/UCIe, DDR, security, and compute interfaces. Define SoC architecture, optimize power, performance, and area, support timing closure through tapeout, package customer design releases, and debug across the hardware and software stack. The role requires hands-on front-end ASIC/SoC experience, SystemVerilog or Verilog proficiency, computer architecture expertise, and subsystem knowledge.

Lead the architecture and development of SoC-level UVM verification environments for GPNPU-based processors. Create test plans, directed and randomized tests, assembly/C++ programs, and co-simulation pipelines. Verify SoC subsystems and third-party IP such as NoC, PCIe/UCIe, and DDR using VCS, SystemVerilog/Verilog, Python, and coverage metrics. Collaborate with architecture, hardware, and software teams to achieve comprehensive verification coverage before tapeout.

Lead end-to-end ISO 26262 functional safety certification for Quadric’s compiler and SDK software stack. Define compliant development processes, oversee TVM and LLVM backend qualification, implement MISRA-C/C++, testing, and requirements traceability, and produce safety documentation. Partner with OEM and Tier-1 automotive customers on safety requirements and system-level certification. The role also supports cybersecurity capability reporting and safety reviews for AI accelerator software.

Design and optimize deep learning compiler infrastructure for Quadric’s edge AI processor. Develop MLIR, TVM, and LLVM optimization passes, lower models from PyTorch, TensorFlow, and ONNX, implement graph transformations and quantization, optimize latency and memory usage, and collaborate on hardware-software co-design. The role also involves compiler validation, simulator development, FPGA/ASIC bring-up, and supporting advanced Transformer and vision models.