Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.
Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.
The OpportunityQuadric is building a revolutionary new processor-based SoC architecture. As a Senior SoC Design Verification Engineer, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.
Architect and build novel, scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.
Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.
Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.
Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.
Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.
Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.
Within your first 6–12 months, you'll:
Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment.
Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks.
Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.
Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.
Deep expertise in UVM methodology and leading SoC-level verification practices.
Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.
Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.
In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our India-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:
Medical, dental, and vision insurance
Equity with the business
Paid Parental Leave
PF Retirement Plan
Flexible PTO
Winter holiday shutdown
Catered lunch each day in our office
Downtown Pune office location, close to shops, cafes, and local amenities
Collaborative, low-ego culture with significant ownership and impact
A work culture focused on innovative disruption
If this role resonates with you, we encourage you to apply even if your experience does not perfectly match every qualification. We value potential, curiosity, and a willingness to learn just as much as direct experience.
Quadric is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, sexual orientation, gender identity, marital status, medical condition, or any other characteristic protected by applicable federal, state, or local law
E-Verify and Right to Work NoticesQuadric participates in the E-Verify program to confirm employment eligibility for U.S.-based roles. As part of this process, applicants may review the following notices, which explain your rights and our participation in E-Verify. These notices are provided in English and Spanish.
E-Verify Participation Notice (English | Spanish)
Right to Work Notice (English | Spanish)
No action is required from candidates during the application process. These notices are provided for informational purposes only.
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Skills Required
- 5+ years of dedicated design verification experience on complex SoC or ASIC designs
- Deep expertise in UVM methodology and SoC-level verification practices
- Proficiency in SystemVerilog or Verilog
- Assembly programming experience
- Scripting experience with Python
- Hands-on experience verifying SoC subsystems and third-party IP, including NoC, PCIe/UCIe, and DDR
- Strong computer architecture background
- Experience with VCS and Verilog/C co-simulation
What We Do
Quadric develops licensable general-purpose neural processing unit (GPNPU) intellectual property and an accompanying software stack for AI chip designers. Its Chimera architecture combines neural-network inference with conventional C++ DSP and control code on a programmable processor. The company’s technology is designed for efficient AI computing on edge and endpoint devices, including automotive, industrial, robotics, and embedded applications. It aims to empower developers to build real-time intelligent products.
