Teams at NXP Semiconductors

Own end-to-end physical design for advanced SoCs, from RTL through GDSII and silicon delivery. Lead floorplanning, synthesis, place and route, CTS, routing, timing, power, physical verification, and signoff while meeting PPA targets. Drive methodology, automation, advanced-node implementation, team mentoring, cross-functional collaboration, EDA vendor engagement, post-silicon bring-up, yield improvement, and production ramp activities.

Architect and develop system management firmware for NXP i.MX SoCs and development boards. Port firmware to new hardware, integrate it across bootloader, trusted firmware, Linux, and MCU SDK components, and develop tests for coverage and performance. Collaborate with architecture, BSP, and support teams to debug and optimize customer systems. Produce documentation and support materials.

Leads STA and physical design timing closure for complex AI, edge, and automotive processor SoCs. Manages engineers, develops and verifies timing constraints, drives subsystem and full-chip closure, improves timing methodologies, and coordinates with architecture, RTL, DV, DFT, EDA, and global design teams. Requires expertise in advanced timing analysis, crosstalk, noise, OCV, clock behavior, jitter, IR drop, and SPICE analysis, along with technical leadership across multi-site teams.