Jobs at MaxLinear

Lead the architecture, design, implementation, verification, characterization, and debugging of RF, analog, mixed-signal, and digital IC circuits integrated into SoCs. Collaborate with system and product teams on specifications and circuit trade-offs, analyze non-idealities, test designs in the lab, define production test requirements, and report design and evaluation results.

Leads microarchitecture and RTL design for DSP modules, including filters, modulators, demodulators, and custom blocks. Integrates DSP subsystems into SoC platforms and develops ASIC solutions meeting power, performance, and area targets. Performs design verification using SystemVerilog, UVM, Python, or C, along with synthesis and static timing analysis. Collaborates across disciplines to solve complex digital communications and semiconductor design challenges.

Leads full-chip ASIC physical design for large programs, including implementation strategy, PPA optimization, closure, signoff readiness, and tapeout delivery. Defines physical design flows, methodologies, guidelines, and adoption plans; resolves design and flow issues; drives technology adoption and organization-wide improvements. Collaborates with front-end, layout, EDA, and program teams, represents physical design in program forums, maintains vendor relationships, hires and mentors engineers, and coordinates execution across teams.

Leads architecture, microarchitecture, RTL design, and integration of high-performance packet-processing, interface, and system-control blocks in multi-CPU SoCs. Develops scalable ASIC solutions for optical and wireless communications, applies digital design and verification methodologies, translates requirements into PPA-efficient implementations, and supports block verification, synthesis, static timing analysis, and design automation.

Architects, develops, debugs, tests, and maintains digital SOC design methodologies and EDA flows from RTL through GDS. Creates scripts, qualifies commercial EDA tools, verifies flow signoff, and establishes tool regressions. Collaborates with engineering IT, database, technology, and design teams to optimize compute infrastructure and resolve signoff issues. Leads projects, guides engineers, documents methodologies, trains design teams, supports flow setup, and drives consensus across business units and EDA vendors.

Leads development of communications ICs with advanced signal-processing blocks, assigning work, tracking progress, resolving technical issues, and prioritizing resources. Collaborates with RF, ASIC, software, marketing, and customer-facing teams. Mentors staff engineers, drives methodology improvements, creates training, encourages innovation and patents, and occasionally performs design or debugging work. Requires deep communications-system expertise and extensive experience in modulation, coding, SERDES, beamforming, or related technologies.

Develop and maintain automated test frameworks; perform functional, regression, stress, reliability, and performance testing; validate storage, networking, and accelerator software stacks; conduct kernel-level testing and debugging on Linux/BSD; analyze performance bottlenecks using observability tools; and lead technical validation initiatives with cross-functional teams.

Designs, verifies, and tests DSP and signal-impairment correction algorithms for broadband communications SoCs. Defines hardware/software partitioning for DSP, control, and datapath blocks, collaborates with RFIC, ASIC, and firmware teams, and mentors junior engineers through PHY-layer development. The role requires strong communications theory, modem architecture, mathematical, and analytical expertise.

Develops and enhances Voice over IP stacks, telephony DSP and SLIC applications for home gateway platforms. Responsibilities include tuning audio algorithms, debugging software, supporting customer IP integration, building audio-quality monitoring tools, and assisting with deployment, configuration, and QA automation. The role requires expert C programming, Linux kernel and networking experience, SIP/IMS voice signaling and media-processing expertise, real-time communication protocols, and familiarity with telephony standards, packet analysis, and security practices.

Design and verify digital RTL for wireless connectivity SoCs and IPs using VHDL or Verilog. Develop low-power, FPGA-friendly, DFT-compliant designs supporting clock domains, functional modes, and SoC integration. Perform simulation, FPGA prototyping, synthesis, and logic equivalence checks, debug design issues, and collaborate with RTL-to-netlist and backend teams throughout the IC lifecycle.

Develops and tests digital signal processing algorithms for fiber-optic communication systems and semiconductor products. Implements algorithm models in C, C++, and MATLAB, collaborates with hardware, software, and architecture teams, and contributes to systems-on-chip definition. Provides technical leadership in transmission technology, channel coding, system architecture, and partitioning.

Leads end-to-end IC substrate and package layout for complex SoCs and multi-die products, including bump planning, pin assignment, floorplanning, routing, stackup definition, SI/PI optimization, verification, signoff, and manufacturing release. Collaborates with physical design, assembly, reliability, manufacturing, OSAT, and substrate vendors. Designs advanced package architectures and supports tape-out while balancing performance, manufacturability, reliability, and cost. May automate workflows and mentor junior designers.

Leads optical hardware systems applications engineering, including team hiring and mentoring, customer design-in support, technical debugging, product testing, reference designs, documentation, vendor and lab management, and product roadmap support. Partners with sales, FAEs, marketing, and engineering teams to secure design wins, resolve customer issues, validate products, and improve reliability. Requires extensive optical transceiver, analog, RF, high-speed digital, PCB, and hardware/software debugging experience, with up to 30% travel.

Develop, maintain, debug, test, and qualify SoC design methodologies and EDA flows from RTL through GDS. Implement scripting-based workflows, verify flow signoff results, establish tool regressions, and integrate flows with engineering compute infrastructure. Support design engineers by resolving setup issues, documenting methodologies, training teams, and collaborating with IT and database management groups.

Provides technical leadership and architecture for IP, subsystem, and SoC verification. Owns verification strategies, UVM environments, coverage, regression, debug, failure triage, and sign-off. Drives AI-assisted and data-driven automation, partners with design and product teams, and mentors verification engineers. Requires deep ASIC verification expertise, leadership across complex programs, proficiency in SystemVerilog, UVM, Verilog, C/C++, scripting, Linux/Unix, and high-speed protocols.

Develop and validate analog serial transceiver ICs from specifications through production release. Design blocks including op-amps, comparators, references, bandgaps, charge pumps, high-voltage transmitters and receivers, and capless LDOs. Collaborate on layout, integration, design reviews, verification, reliability, yield, post-silicon debugging, system characterization, and productization support.

Leads ASIC design verification across IP, subsystem, and SoC levels. Defines test plans, develops reusable UVM environments, drives functional and code coverage closure, debugs complex issues, and owns verification deliverables through sign-off. Applies AI-assisted workflows to improve test generation, debug, coverage analysis, and regression efficiency. Collaborates with architecture, design, validation, and cross-functional teams while advancing verification automation, quality, and process improvements.

Develop RTL designs for ASIC and FPGA implementations, contribute to architecture and microarchitecture, perform block integration and debug, and support verification, synthesis, timing analysis, and design sign-off. Collaborate across engineering teams, document interfaces, support silicon bring-up and root-cause analysis, evaluate reusable IP, and implement low-power techniques such as clock gating and power optimization.

Develop and test embedded C software for DOCSIS home gateway SDKs in real-time operating systems. Collaborate with architecture and silicon teams, build user-space and kernel modules on ARM and ATOM processors, and solve system-wide issues spanning hardware interfaces, operating systems, networking, and applications. The role also involves using AI-driven development tools, mentoring engineers, and planning and leading projects.

Architects and leads digital verification strategies for complex analog mixed-signal ASIC products. Builds block, cluster, and full-chip UVM environments using constrained-random techniques; develops scoreboards, agents, sequencers, and monitors; debugs RTL and gate simulations; converts tests into ATE patterns; and collaborates with design, system, and test engineering teams to ensure first-silicon success.