Jobs at Majestic Labs AI

Lead cross-functional programs to deploy AI servers from prototype to volume production. Manage roadmaps, suppliers, ODMs, procurement, manufacturing, risk, budgets, and stakeholder communication to ensure on-time, production-ready delivery of compute infrastructure.

Lead architecture and integration of RISC-V-based compute clusters and vector engines for AI acceleration. Define ISA extensions, interconnects, memory hierarchies, scheduling, and cache utilization; collaborate with compiler, ML runtime, RTL, verification, and firmware teams; evaluate performance/power trade-offs; and specify debug, trace, and performance-monitoring features to deliver scalable, power-efficient AI SoC compute subsystems.

Design and implement high-performance kernels for AI primitives (GEMM, attention, normalization, convolution). Optimize throughput, latency, and memory hierarchy across heterogeneous compute units. Integrate kernels with Triton/PyTorch/SYCL, profile and tune with Perfetto/VTune/Tracy, prototype precision formats and stochastic rounding, and contribute micro-architecture feedback. Write reusable C++/CUDA/Triton/LLVM MLIR code.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Perform chip-level and performance verification of custom ASICs. Design end-to-end test flows and methodologies with architects to verify real-world performance. Use simulation tools and UVM environments, implement constrained-random and coverage-driven tests, and collaborate across teams and vendors to validate silicon.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Design, develop, and optimize core components of an AI-driven software stack. Implement API layers, command pipelines, and memory management; collaborate with hardware and kernel teams; debug across user-to-hardware layers; and optimize for performance and throughput.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Develop and maintain system-level performance simulators and models for AI/data-intensive workloads; characterize real workloads (LLMs, GNNs, graph analytics); model memory, interconnect, and scheduling behavior; evaluate architectural trade-offs and produce quantitative comparisons; collaborate with hardware architects, compiler/runtime teams, partners, and stakeholders; translate performance modeling into clear narratives for technical and executive audiences.

Design, implement, and optimize compiler components for AI models targeting CPUs, GPUs, and custom accelerators. Enhance PyTorch Inductor/Dynamo, Triton, LLVM, and MLIR toolchains; create IRs, codegen passes, and performance optimizations; profile and tune kernels; and contribute to open-source projects.

Lead the design and integration of the SoC management subsystem: define ARM core integration, PCIe and DDR/LPDDR interfaces, peripheral/control buses, scheduler and interrupt schemes, debug/trace infrastructure, and collaborate across RTL, firmware, verification, and board teams to meet performance, power, and area targets.

Provide high-level executive support to founders (calendar, travel, expenses, communications) and manage office operations, vendor relationships, facilities, budgets, onboarding, and culture-building events for a 25-50 person startup.

Lead the architectural design of SoC networking, SmartNIC/NIC and switch interface IPs for AI accelerators. Define scale-up/scale-out topologies, hardware offloads for collective operations, optimize transport protocols and congestion control, run performance modeling and simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead architectural design of SoC networking engines, SmartNIC/NIC and switch IPs for AI servers. Define intra-node and inter-node topologies, design hardware offloads for collective operations, optimize transport protocols and congestion control, run performance/cycle-accurate simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead end-to-end technical programs across compiler infrastructure, AI kernel development, GPU runtime, hardware integration, and data center deployments. Break down complex system architecture into milestones, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to ensure production-ready server solutions.

Lead end-to-end technical programs across compiler, kernel, runtime, hardware integration, and data center deployment. Translate system architectures into schedules, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to deliver production-ready server solutions.

Lead end-to-end signal and power integrity for high-speed interconnects across architecture, pre-silicon modeling, silicon bring-up, validation, and high-volume manufacturing. Perform channel modeling, EM/field solver correlation to lab measurements, PDN analysis, and SI/PI co-design. Support debug, define design rules with cross-functional teams, lead DVT/PVT to production, and improve internal methodology and tooling.

Lead architecture and end-to-end firmware design for server platforms, including OOB management, power and thermal control, boot sequencing, firmware update pipelines, and firmware security. Collaborate with silicon and hardware teams, drive silicon bring-up, produce architecture/spec documents, and enforce secure firmware practices.