Jobs at Majestic Labs AI

Lead architecture and integration of RISC-V-based compute clusters and vector engines for AI acceleration. Define ISA extensions, interconnects, memory hierarchies, scheduling, and cache utilization; collaborate with compiler, ML runtime, RTL, verification, and firmware teams; evaluate performance/power trade-offs; and specify debug, trace, and performance-monitoring features to deliver scalable, power-efficient AI SoC compute subsystems.

Design and implement high-performance kernels for AI primitives (GEMM, attention, normalization, convolution). Optimize throughput, latency, and memory hierarchy across heterogeneous compute units. Integrate kernels with Triton/PyTorch/SYCL, profile and tune with Perfetto/VTune/Tracy, prototype precision formats and stochastic rounding, and contribute micro-architecture feedback. Write reusable C++/CUDA/Triton/LLVM MLIR code.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Perform chip-level and performance verification of custom ASICs. Design end-to-end test flows and methodologies with architects to verify real-world performance. Use simulation tools and UVM environments, implement constrained-random and coverage-driven tests, and collaborate across teams and vendors to validate silicon.

Build and operate developer infrastructure: CI/CD pipelines, dev environments, containerized builds, and internal deployments. Improve build/test speed, observability, and production-representative dev systems while partnering with compiler, runtime, kernel, and hardware teams.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Lead strategy and execution for silicon, IP, and system partnerships. Cultivate vendor relationships, manage RFQs, negotiate complex technology and sourcing deals, establish supply chain agreements, and align partnerships with engineering and product priorities while interfacing with founders and leadership.

Design, develop, and optimize core components of an AI-driven software stack. Implement API layers, command pipelines, and memory management; collaborate with hardware and kernel teams; debug across user-to-hardware layers; and optimize for performance and throughput.

Lead definition and implementation of the SoC management subsystem for an AI accelerator: integrate ARM cores, PCIe, DDR/LPDDR, peripherals, debug/trace infrastructure, and design control/interrupt/driver interfaces while coordinating RTL, firmware, verification, and board teams to meet performance, power, and area targets.

Design and optimize high-performance compute kernels for AI primitives (GEMM, attention, convolution), profile and tune across heterogeneous hardware, collaborate with compiler/runtime teams (Triton, PyTorch, SYCL), prototype precision formats, and contribute micro-architecture feedback while writing reusable C++/CUDA/Triton/MLIR code.

Provide high-level executive support to founders (calendar, travel, expenses, correspondence) while managing office operations, vendor relationships, facilities, HR logistics, budget oversight, event planning, and new-hire onboarding for a 25–50 person startup.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Develop and maintain system-level performance simulators and models for AI/data-intensive workloads; characterize real workloads (LLMs, GNNs, graph analytics); model memory, interconnect, and scheduling behavior; evaluate architectural trade-offs and produce quantitative comparisons; collaborate with hardware architects, compiler/runtime teams, partners, and stakeholders; translate performance modeling into clear narratives for technical and executive audiences.

Design, implement, and optimize compiler components for AI workloads using PyTorch, Triton, LLVM, and MLIR. Build IRs, codegen passes, and performance-tuned kernels for CPUs, GPUs, and custom accelerators. Contribute upstream to open-source projects and collaborate cross-functionally to enable scalable, high-performance deployment across diverse hardware.

Design, develop, and maintain core components of an AI-driven software stack enabling efficient communication with hardware. Implement API layers, command submission pipelines, and memory management; collaborate with hardware architects and kernel developers; debug across user-to-hardware stack and optimize for performance and throughput.

Design, implement, and optimize compiler components for AI models targeting CPUs, GPUs, and custom accelerators. Enhance PyTorch Inductor/Dynamo, Triton, LLVM, and MLIR toolchains; create IRs, codegen passes, and performance optimizations; profile and tune kernels; and contribute to open-source projects.

Build and operate developer infrastructure: CI/CD pipelines, dev environments, containerized builds, internal deployments, observability, and production-representative dev systems to accelerate engineers across compiler, runtime, kernel, and hardware teams.