Jobs at Majestic Labs AI

Design, develop, and optimize compiler components for AI workloads across CPUs, GPUs, and custom accelerators. Enhance PyTorch Inductor, Triton, LLVM, and MLIR toolchains; create custom intermediate representations, code-generation passes, and optimization strategies; tune computational kernels for performance; and contribute to open-source compiler projects.

Manage vendor backend execution and NPI for data-center AI chips, coordinating schedules from RTL freeze and physical implementation through tapeout, post-silicon characterization, qualification, validation, and high-volume production. The role bridges hardware design, backend engineering, DFT, and product engineering while driving technical trade-offs and cross-functional execution.

Manage vendor backend execution and NPI for data-center AI chips, coordinating schedules from RTL freeze and physical implementation through tapeout, post-silicon characterization, qualification, validation, and high-volume production. The role bridges hardware design, backend implementation, DFT, and product engineering while challenging technical trade-offs and driving cross-functional execution.

Own end-to-end signal and power integrity for high-speed links from architecture and pre-silicon modeling through silicon bring-up, validation, DVT/PVT, and high-volume manufacturing. Analyze SerDes, PCIe, DDR, and chip-to-chip interfaces; perform EM, channel, margin, and PDN modeling; correlate simulations with lab measurements; debug failures; establish design rules and test limits; and collaborate with ASIC, package, PCB, manufacturing, and test teams.

Lead architecture and integration of RISC-V-based compute clusters and vector engines for AI acceleration. Define ISA extensions, interconnects, memory hierarchies, scheduling, and cache utilization; collaborate with compiler, ML runtime, RTL, verification, and firmware teams; evaluate performance/power trade-offs; and specify debug, trace, and performance-monitoring features to deliver scalable, power-efficient AI SoC compute subsystems.

Design and implement high-performance kernels for AI primitives (GEMM, attention, normalization, convolution). Optimize throughput, latency, and memory hierarchy across heterogeneous compute units. Integrate kernels with Triton/PyTorch/SYCL, profile and tune with Perfetto/VTune/Tracy, prototype precision formats and stochastic rounding, and contribute micro-architecture feedback. Write reusable C++/CUDA/Triton/LLVM MLIR code.

Perform chip-level and performance verification of custom ASICs. Design end-to-end test flows and methodologies with architects to verify real-world performance. Use simulation tools and UVM environments, implement constrained-random and coverage-driven tests, and collaborate across teams and vendors to validate silicon.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Design, develop, and optimize core components of an AI-driven software stack. Implement API layers, command pipelines, and memory management; collaborate with hardware and kernel teams; debug across user-to-hardware layers; and optimize for performance and throughput.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Develop and maintain system-level performance simulators and models for AI/data-intensive workloads; characterize real workloads (LLMs, GNNs, graph analytics); model memory, interconnect, and scheduling behavior; evaluate architectural trade-offs and produce quantitative comparisons; collaborate with hardware architects, compiler/runtime teams, partners, and stakeholders; translate performance modeling into clear narratives for technical and executive audiences.

Design, implement, and optimize compiler components for AI models targeting CPUs, GPUs, and custom accelerators. Enhance PyTorch Inductor/Dynamo, Triton, LLVM, and MLIR toolchains; create IRs, codegen passes, and performance optimizations; profile and tune kernels; and contribute to open-source projects.

Lead the design and integration of the SoC management subsystem: define ARM core integration, PCIe and DDR/LPDDR interfaces, peripheral/control buses, scheduler and interrupt schemes, debug/trace infrastructure, and collaborate across RTL, firmware, verification, and board teams to meet performance, power, and area targets.

Lead the architectural design of SoC networking, SmartNIC/NIC and switch interface IPs for AI accelerators. Define scale-up/scale-out topologies, hardware offloads for collective operations, optimize transport protocols and congestion control, run performance modeling and simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead architectural design of SoC networking engines, SmartNIC/NIC and switch IPs for AI servers. Define intra-node and inter-node topologies, design hardware offloads for collective operations, optimize transport protocols and congestion control, run performance/cycle-accurate simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead end-to-end technical programs across compiler infrastructure, AI kernel development, GPU runtime, hardware integration, and data center deployments. Break down complex system architecture into milestones, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to ensure production-ready server solutions.

Lead end-to-end technical programs across compiler, kernel, runtime, hardware integration, and data center deployment. Translate system architectures into schedules, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to deliver production-ready server solutions.