Teams at Majestic Labs AI

Lead architecture and integration of RISC-V-based compute clusters and vector engines for AI acceleration. Define ISA extensions, interconnects, memory hierarchies, scheduling, and cache utilization; collaborate with compiler, ML runtime, RTL, verification, and firmware teams; evaluate performance/power trade-offs; and specify debug, trace, and performance-monitoring features to deliver scalable, power-efficient AI SoC compute subsystems.

Design and implement high-performance kernels for AI primitives (GEMM, attention, normalization, convolution). Optimize throughput, latency, and memory hierarchy across heterogeneous compute units. Integrate kernels with Triton/PyTorch/SYCL, profile and tune with Perfetto/VTune/Tracy, prototype precision formats and stochastic rounding, and contribute micro-architecture feedback. Write reusable C++/CUDA/Triton/LLVM MLIR code.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.