Jobs at Fortell Research Inc

Own mechanical design for miniature hearing aids and related tooling from concept through high-volume production. Responsibilities include designing precision molded and machined parts, performing tolerance analysis, prototyping, developing fixtures and test equipment, running reliability validation, managing overseas suppliers and contract manufacturers, troubleshooting production yields, and maintaining mechanical project schedules. The role requires extensive experience with miniaturized electromechanical products, injection molding, GD&T, supplier management, and volume launches.

Own the commercial technology roadmap for Fortell’s hearing-aid experience, from identifying patient and clinic problems through launch and measurement. Define product experiences, prioritize scope and sequencing, collaborate closely with engineering, analyze product data, and scale internal tooling and software capabilities. The role requires hands-on clinic engagement, strong technical judgment, clear writing, and balancing patient needs with operational constraints in a regulated hardware-software environment.

Supports finance operations by processing invoices, purchase orders, expenses, company cards, vendor records, and monthly close activities. Manages NYC office logistics, supplies, deliveries, guests, equipment, vendors, and office relocation planning. Assists with onboarding, personnel records, recruiting logistics, and team events. Improves internal processes by creating workflows, checklists, trackers, and documentation.

Lead RF development and bring-up for ear-worn hearing aid products: design antenna and matching networks, optimize link budgets for Bluetooth/BLE/NFMI, collaborate on schematic and PCB layout (Altium), run RF simulation and bench/chamber testing (CST Studio and RF test gear), prototype and troubleshoot, and support production validation and regulatory testing.

Lead full-chip DFT architecture and implementation including scan, compression, MBIST/BIST, ATPG vector generation, gate-level verification, and silicon debug. Collaborate with STA, physical design, memory compiler, and test teams to ensure production-ready silicon with high test coverage and diagnostic capability, and support bring-up and debug on silicon.

Execute synthesis, place-and-route and STA for ASIC partitions from RTL to silicon. Collaborate with architects, RTL designers and DFT engineers to close EM/IR, LEC and physical verification signoff. Improve physical design methodologies (synthesis, PnR, EMIR, PDN), troubleshoot flows and work with EDA vendors to resolve issues while meeting tight schedules and low-power goals.