Jobs at Eridu AI

Lead hands-on verification for complex networking ASICs from strategy and test planning through coverage closure and tape-out. Develop SystemVerilog/UVM environments, testbenches, sequences, checkers, scoreboards, and constrained-random tests. Debug RTL and simulation failures, drive functional/code/assertion coverage, and collaborate with architecture, RTL, physical design, firmware, emulation, and silicon teams. Establish quality gates, manage verification risks, support full-chip validation, and ensure tape-out and post-silicon readiness.

Designs reliable board-mounted power solutions for AI data center technologies, including voltage regulation, power conversion, distribution, and power management circuits. Responsibilities include circuit simulation, PCB layout collaboration, EMI and noise reduction, component selection, supplier coordination, and validation testing for efficiency, transient response, ripple, noise, and thermal performance. The role is based in Taipei with occasional travel to Hsinchu.

Design and deliver complex hardware systems and sub-assemblies from concept through production. Responsibilities include defining specifications, architecting systems, evaluating suppliers, guiding schematic and layout reviews, developing EDVT/MDVT and EMI/EMC test plans, and validating prototypes in the lab. The role requires cross-functional collaboration across architecture, semiconductor, software, manufacturing, and external partners, with emphasis on high-speed optical and electrical I/O, signal and power integrity, thermal performance, reliability, compliance, cost, and schedule.

Lead system-level hardware development for AI data center infrastructure, from hardware definition and detailed design through qualification and production release. Lead the Taiwan engineering team and coordinate with ODM partners on schematics, layouts, manufacturability, bring-up, signal and power integrity, compliance testing, root-cause analysis, and corrective actions. Collaborate globally to deliver reliable, cost-effective hyperscale systems and sub-assemblies.

Design rack-mounted computing hardware, including sheet-metal chassis, structural frames, board mounts, card cages, PSU structures, cable management, and thermal integration components. Drive DFM and DFA through manufacturing-ready CAD and drawings, collaborate with ODM partners, review designs and tolerance analyses, manage costs, support prototype builds and EVT/DVT validation, and help deliver products through production ramp.

Design and deliver advanced optical interconnect subsystems from concept through production, integrating optics, electronics, packaging, mechanics, thermal systems, and power delivery. Lead partner design reviews, qualification, testing, and production transition. Build and automate the optical lab, develop measurement workflows, run electro-optical experiments, and create MATLAB or Python tools for experiment control, analysis, and simulation correlation.

Own end-to-end physical layout and routing for high-density, multi-die organic substrates, packages, modules, and high-speed interface boards. Perform feasibility studies, signal and power integrity implementation, package-to-board co-design, constraint and library management, design checks, manufacturing documentation, and release activities. Collaborate with ASIC, mechanical, SI/PI, manufacturing, foundry, substrate, OSAT, and fabrication partners to resolve manufacturability issues and deliver designs to production.

Own optical test and measurement system development for advanced optical communication systems. Build and automate the optical lab, design experiments, characterize optical and electro-optical systems, analyze measurement data, and guide system design decisions. Drive OSAT and ODM partners through design reviews, testing, qualification, and production transition. Develop MATLAB and Python tools for experiment control, data analysis, scan automation, and sim-to-measurement correlation while meeting quality, cost, and schedule goals.

Leads embedded software and firmware development for high-speed SerDes PHYs supporting Ethernet, PCIe, and UCIe interfaces. Responsibilities include PHY initialization, link training, equalization, calibration, diagnostics, characterization, production testing, health monitoring, and failure analysis. The role spans pre- and post-silicon bring-up, laboratory validation, system-level signal integrity, and optimization across operating conditions. It also defines reusable software architecture, creates technical documentation, mentors engineers, and serves as the technical authority for SerDes software and system bring-up.

Lead product marketing for AI data center networking solutions. Define positioning, messaging, value propositions, competitive intelligence, thought leadership, content, product launches, and sales enablement. Collaborate with product management, engineering, sales, and marketing to translate complex technical capabilities into differentiated customer outcomes for hyperscalers, neoclouds, and other large service providers.

Leads hardware engineering for Eridu’s AI data center infrastructure solutions spanning silicon, packaging, and systems. The posting provides no specific responsibilities, minimum qualifications, preferred qualifications, technologies, travel requirements, or clearance requirements. The manager will help advance high-performance infrastructure products intended to improve AI data center communication, GPU utilization, cost efficiency, power consumption, and reliability.

This listing collects unsolicited applications into a talent pool for future openings at Eridu AI. Candidates submit their information; the company will contact applicants if a role matches their skills and interests.

The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.

Develop board-mounted power solutions for data center technologies, including voltage regulation, power conversion, distribution, DC-DC converters, AC-DC modules, and power management circuits. Model performance using circuit simulation tools, collaborate on PCB layout, minimize EMI and noise, select components with suppliers, and create test procedures validating efficiency, transient response, ripple, noise, and thermal performance.

Define and implement design-for-test architecture for multi-chip SoCs, including scan, BIST, memory repair, boundary scan, OCC, LBIST, and ATPG. Develop synthesis constraints, supervise ATPG generation, and achieve high scan and at-speed scan coverage. Perform RTL and gate-level simulation using DFT and synthesis tools while collaborating on low-power, high-performance designs for advanced 7nm-or-below technologies.

Develop and integrate OCP SAI with SONiC, enhance control plane stack, ensure optimal SDK performance, and create automated test tools.

Design and develop Linux-based BSP for hardware platforms, focusing on secure boot, hardware initialization, and integration with platform services. Collaborate across teams to optimize performance and support production readiness.

Develop SDK bridging hardware and software for networking. Ensure performance of switch ASICs with a focus on L2/L3 protocols and embedded systems.

Lead the QA strategy for Network SDK, design test frameworks, mentor engineers, validate core SDK layers, and ensure high-quality releases.

Lead the design and development of SDK for Eridu's switch ASICs, ensuring performance and production readiness. Oversee software interfaces for dataplane operations and mentor junior engineers.