The Verification Engineer will develop verification infrastructure for ASICs, ensure compliance with standards, perform simulations, and uphold verification quality in AI networking solutions.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

Lead the design and development of a Software Development Kit (SDK) for networking ASICs, collaborating with teams to ensure performance and production readiness.

The Senior Hardware Design Engineer will design and produce complex hardware systems, ensuring performance, cost-effectiveness, and reliability while collaborating across teams.

Design and implement high-speed networking solutions focusing on latency optimization and memory management. Perform testing, optimization, and troubleshoot complex networking issues.

Lead the architecture and integration of SAI with SONiC, work on SDK development, collaborate across teams, and develop automated tests.

The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

As an RTL Engineer, the role involves designing and implementing networking ASICs, optimizing performance, supporting various protocols, and collaborating across teams for troubleshooting and debugging.

The role involves validating Linux-based Board Support Packages (BSPs), developing test plans, automating tests, and collaborating with developers and engineers.

Lead the DFT architecture of multi-chip systems, oversee test design functions, manage ATPG generation, and ensure high coverage goals. Collaborate with advanced DFT techniques, drive performance, and utilize various CAD tools.

Responsible for developing diagnostic software and tools for hardware validation, collaborating with teams for board validation, and conducting root cause analysis.

The Staff RTL Engineer will design high-speed networking devices, optimize memory management, ensure compliance with standards, and collaborate with various teams for performance optimization and troubleshooting.

The role involves designing and architecting microarchitecture for Ethernet packet processing, collaborating with teams, conducting feasibility studies, and verifying designs for performance optimization.

Define physical assembly of SOC, perform P&R, timing, and design analysis. Collaborate with micro-architects on performance tradeoffs and validate design processes.

Lead the architecture and development of SAI with SONiC, manage SDK development, and ensure integration with hardware, while overseeing automated tests and collaborating with teams.

Design and implement high-speed networking chips focusing on packet buffering, performance optimization, and protocol support, ensuring compliance with standards and conducting thorough testing.

The Hardware Engineer will be responsible for developing systems and sub-assemblies from concept to production, involving hardware definition, design, qualification, and collaboration with multiple teams.

Lead the design and implementation of packet processing architectures for high-performance networking ASICs, collaborating with various engineering teams to meet system requirements and optimize performance.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.