The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.

The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.

Seeking a Senior Power Engineer to design high-efficiency power delivery solutions for AI infrastructure, focusing on DC-DC conversion and power distribution for high-performance systems.

The Verification Engineer will develop verification infrastructure for ASICs, ensure compliance with standards, perform simulations, and uphold verification quality in AI networking solutions.

Lead SoC physical design including P&R, floorplanning, clocking, timing and power closure. Develop methodologies, run signoff flows (timing, power, EM/IR, PDV), collaborate with micro-architects for PPA tradeoffs, and drive tape-out readiness for deep-submicron (7nm or below) designs.

Lead the QA strategy for Network SDK, design test frameworks, mentor engineers, validate core SDK layers, and ensure high-quality releases.

Lead the design and development of SDK for Eridu's switch ASICs, ensuring performance and production readiness. Oversee software interfaces for dataplane operations and mentor junior engineers.

Lead the development and integration of OCP SAI with SONiC, requiring expertise in programming, SDK development, and networking protocols.

The Executive Administrator will support the executive team with administrative tasks, manage schedules, coordinate travel, and handle communications.

Lead design and implementation of Linux BSP and low-level platform software including bootloaders, kernel subsystems, and drivers. Architect and implement secure boot and TPM integration. Drive hardware bring-up, diagnostics, platform SDKs, and control-plane integration with SONiC or custom APIs. Support production readiness, debugging, and long-term maintainability.

The role involves contributing to the development of AI infrastructure solutions that enhance performance in AI data centers, focusing on silicon, software, and system innovations.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

Lead the architecture and integration of SAI with SONiC, work on SDK development, collaborate across teams, and develop automated tests.

The role involves validating Linux-based Board Support Packages (BSPs), developing test plans, automating tests, and collaborating with developers and engineers.

The role involves developing predictive models for complex mechanical systems, conducting simulations, validating experiments, and leading mechanical design for semiconductor packaging. Responsibilities include material selection, cross-functional collaboration, and influencing system architectures.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

Lead the design and development of a Software Development Kit (SDK) for networking ASICs, collaborating with teams to ensure performance and production readiness.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.