Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

As an RTL Engineer, the role involves designing and implementing networking ASICs, optimizing performance, supporting various protocols, and collaborating across teams for troubleshooting and debugging.

Lead the architecture and integration of SAI with SONiC, work on SDK development, collaborate across teams, and develop automated tests.

The Verification Engineer will develop verification infrastructure for ASICs, ensure compliance with standards, perform simulations, and uphold verification quality in AI networking solutions.

The role involves validating Linux-based Board Support Packages (BSPs), developing test plans, automating tests, and collaborating with developers and engineers.

Responsible for developing diagnostic software and tools for hardware validation, collaborating with teams for board validation, and conducting root cause analysis.

The role involves designing and architecting microarchitecture for Ethernet packet processing, collaborating with teams, conducting feasibility studies, and verifying designs for performance optimization.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

Lead the design and development of a Software Development Kit (SDK) for networking ASICs, collaborating with teams to ensure performance and production readiness.

Define physical assembly of SOC, perform P&R, timing, and design analysis. Collaborate with micro-architects on performance tradeoffs and validate design processes.

Lead the architecture and development of SAI with SONiC, manage SDK development, and ensure integration with hardware, while overseeing automated tests and collaborating with teams.

The Hardware Engineer will be responsible for developing systems and sub-assemblies from concept to production, involving hardware definition, design, qualification, and collaboration with multiple teams.

The Senior Hardware Design Engineer will design and produce complex hardware systems, ensuring performance, cost-effectiveness, and reliability while collaborating across teams.

Lead the design and implementation of packet processing architectures for high-performance networking ASICs, collaborating with various engineering teams to meet system requirements and optimize performance.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

Lead the design and development of an SDK for ASICs, ensuring high-performance operations and integration with software ecosystems. Mentor juniors and establish best practices.

The role involves leading the design and implementation of high-speed clock distribution networks for SoC designs, ensuring performance and synchronization across multiple modules, and managing the process from architecture to tape-out.

The Synthesis Engineer will define and implement networking ICs, develop synthesis flows, collaborate with micro-architects on PPA tradeoffs, and assist in functional sign-off for AI networking solutions.

The Technical Leader for Network SDK QA will manage the quality and reliability of the platform software, defining QA strategy, designing test frameworks, and mentoring QA engineers. Responsibilities include leading testing processes, collaborating cross-functionally, and driving automation coverage.