Jobs at Eridu AI

This listing collects unsolicited applications into a talent pool for future openings at Eridu AI. Candidates submit their information; the company will contact applicants if a role matches their skills and interests.

The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.

Develop and integrate OCP SAI with SONiC, enhance control plane stack, ensure optimal SDK performance, and create automated test tools.

Design and develop Linux-based BSP for hardware platforms, focusing on secure boot, hardware initialization, and integration with platform services. Collaborate across teams to optimize performance and support production readiness.

Develop SDK bridging hardware and software for networking. Ensure performance of switch ASICs with a focus on L2/L3 protocols and embedded systems.

Design and deliver system-level hardware from concept to production for high-speed optical and electrical I/O systems. Define hardware specifications, architect designs, develop de-risk plans, collaborate with partners on schematic/layout, create test plans (EDVT/MDVT/EMI), and validate prototypes in lab.

Lead the QA strategy for Network SDK, design test frameworks, mentor engineers, validate core SDK layers, and ensure high-quality releases.

Lead the design and development of SDK for Eridu's switch ASICs, ensuring performance and production readiness. Oversee software interfaces for dataplane operations and mentor junior engineers.

Lead the development and integration of OCP SAI with SONiC, requiring expertise in programming, SDK development, and networking protocols.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The RTL Engineer will collaborate on the design and productization of Ethernet devices, perform RTL coding, debugging, and post-silicon validation with a focus on networking ICs.

The Engineering Program Manager will lead complex product development programs, manage cross-functional execution, coordinate schedules, and drive communication among teams and external partners.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

The role involves validating Linux BSPs for stability and performance, developing test plans, automating tests, collaborating with teams, and ensuring quality for next-gen networking products.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

The role involves post-silicon bring-up, debugging, and validation of ASICs, focusing on diagnostic infrastructures and automation frameworks.