Teams at Eridu AI

Design and implement high-speed networking ASIC RTL, focusing on packet buffering, queuing, scheduling, QoS, latency optimization, and pipelining. Develop support for Ethernet, IP, and UCIe protocols; implement and test ASIC designs; collaborate with verification, architecture, hardware, and firmware teams; and troubleshoot complex packet-queuing and networking issues.

Lead hands-on verification for complex networking ASICs from strategy and test planning through coverage closure and tape-out. Develop SystemVerilog/UVM environments, testbenches, sequences, checkers, scoreboards, and constrained-random tests. Debug RTL and simulation failures, drive functional/code/assertion coverage, and collaborate with architecture, RTL, physical design, firmware, emulation, and silicon teams. Establish quality gates, manage verification risks, support full-chip validation, and ensure tape-out and post-silicon readiness.

Designs reliable board-mounted power solutions for AI data center technologies, including voltage regulation, power conversion, distribution, and power management circuits. Responsibilities include circuit simulation, PCB layout collaboration, EMI and noise reduction, component selection, supplier coordination, and validation testing for efficiency, transient response, ripple, noise, and thermal performance. The role is based in Taipei with occasional travel to Hsinchu.