As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.

The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.

The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.