Search the 7 jobs at Eliyan Corporation

Join the leading chiplet startup as a Design Verification Engineer/Lead. Responsibilities include verifying Analog Mixed Signal designs, defining test plans, authoring test benches, creating assertions, and collaborating with designers. Ideal candidates hold a BS EE with 5 years of experience and expertise in UVM and SystemVerilog.

Join a chiplet startup as a Senior Analog Design Engineer, responsible for developing custom analog mixed-signal blocks for high-speed wireline links. Collaborate with digital teams for optimization and validation of designs. Requires 8 years experience in high-speed SerDes components and proficiency in Cadence Virtuoso and high-speed layout considerations.

As a Signal and Power Integrity Engineer, responsible for providing packaging solutions for chiplet interconnects in a fast-paced early-stage startup creating technologies. Work closely with analog circuit designers, conduct simulations, understand manufacturing design rules, and perform lab measurements.

Join the leading chiplet startup as a Senior Analog Design Engineer. Responsible for developing custom analog mixed-signal blocks for high-speed wireline links and collaborating with digital teams to optimize designs. Must have a minimum of eight years of experience in designing high-speed SerDes components and proficiency in Cadence Virtuoso design environment.

Join the leading chiplet startup as a Physical Design Engineer responsible for establishing methodologies for high-speed block design, integrating analog/mixed signal blocks, developing correct-by-construction designs, and automating flows for efficiency. Requires expertise in physical design, timing, and scripting.

Join the leading chiplet startup as a Digital Design Engineer. Define, implement, and ensure correctness of novel RTL for major blocks in chiplet based systems. Collaborate with cross-functional team to innovate high-volume, high-performance products. Responsibilities include RTL design, specification writing, formal verification, and silicon bring-up. Requires BS EE with 5 years of experience.

Lead a team of physical design engineers developing chiplets and chiplet IPs, define and implement innovative design methodologies, collaborate with cross-functional teams to deliver customer-ready products, automate flows and processes to maximize efficiency, develop flows for identifying weaknesses in implementations, and automate sign-off tools for timing, DFM, reliability, EM/IR.