Jobs at Edgecortix

Design and verify ASIC hardware, optimize designs for power and performance, collaborate on architectural decisions, and support integration activities.

Lead Japan/APAC marketing communications, PR, events, and customer engagement for a fabless AI semiconductor company. Manage bilingual content, HubSpot-driven nurture campaigns, event execution, PR coordination, demo environment upkeep, and cross-functional marketing collateral to support global awareness and GTM initiatives.

The Senior Accountant will manage financial reporting, closing processes, budgeting, and audits, while building scalable accounting systems in a fast-paced startup environment.

This internship opportunity allows candidates to gain experience in an on-site environment, specifically at the Tokyo or India office, under a flexible schedule.

You will design, develop, and maintain software for Edge AI devices, leveraging robust debugging skills and collaborating on innovative technologies.

Manage ASIC program execution across schedule, performance, power, cost, and quality. Track risks, enforce change control, run milestone reviews, report to senior management, and coordinate cross-functional teams to ensure timely delivery of SOC products.

Lead and execute the ASIC program to deliver SOCs on schedule, on budget, and to quality targets. Manage risks, dependencies, change control, milestones, metrics, and cross-functional coordination across design, verification, physical design, DFT, EDA partners, HW/SW, and validation. Report to senior management and ensure predictable execution.

Collaborate with engineers to extend compiler/toolchain for high-performance ML model deployment on AI hardware. Requires significant software engineering experience and knowledge of ML.

You will develop and optimize machine learning models for EdgeCortix's hardware, collaborating with engineers to meet AI performance goals.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.

Responsible for ASIC implementation tasks including synthesis, timing constraints, ECOs, validation, and supporting RTL development and physical design activities.

Own the integration of IP into ASSP/SOC, including RTL design, synthesis, timing analysis, and verification infrastructure development. Requires expertise in Verilog and C/C++.

Design and verify ASIC chips by implementing RTL, handling synthesis, power estimation, and collaborating on architecture for AI systems.

The Physical Design Engineer will implement AI acceleration SoCs, focusing on RTL-to-GDSII flows, synthesis, timing analysis, and collaboration with internal and external teams.

Develop and execute test automation for AI/ML software releases, troubleshoot issues, collaborate across teams, and maintain QA infrastructure.

The Design Verification Engineer will enhance verification environments for AI SoCs, collaborate on infrastructure, and automate tool flows for verification.