Jobs at Edgecortix

Lead SoC RTL design, integration, implementation, and quality checks across frontend, DFT, verification, and physical design. Own PPA, constraints, clocking, boot, low-power architecture, interfaces, memory subsystems, and chip-level integration. Collaborate with global architecture and engineering teams, mentor engineers, evaluate IPs, support production-quality silicon, and influence technical strategy. The role requires leadership in SoC design and verification, advanced connectivity and processor architectures, and expertise in lint, CDC, RDC, power-aware design, chiplets, and die-to-die technologies.

This internship opportunity allows candidates to gain experience in an on-site environment, specifically at the Tokyo or India office, under a flexible schedule.

Lead end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and IP blocks. Drive PPA optimization, synthesis, floorplanning, placement, CTS, routing, STA, power planning (UPF), timing closure and sign-off using Synopsys/Cadence tools. Define methodologies, collaborate cross-functionally, coordinate external implementation partners, and mentor junior engineers to ensure high-quality tape-outs and continuous process improvements.

You will design, develop, and maintain software for Edge AI devices, leveraging robust debugging skills and collaborating on innovative technologies.

Manage ASIC program execution across schedule, performance, power, cost, and quality. Track risks, enforce change control, run milestone reviews, report to senior management, and coordinate cross-functional teams to ensure timely delivery of SOC products.

Collaborate with engineers to extend compiler/toolchain for high-performance ML model deployment on AI hardware. Requires significant software engineering experience and knowledge of ML.

You will develop and optimize machine learning models for EdgeCortix's hardware, collaborating with engineers to meet AI performance goals.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.

Responsible for ASIC implementation tasks including synthesis, timing constraints, ECOs, validation, and supporting RTL development and physical design activities.

Own the integration of IP into ASSP/SOC, including RTL design, synthesis, timing analysis, and verification infrastructure development. Requires expertise in Verilog and C/C++.

Design and verify ASIC chips by implementing RTL, handling synthesis, power estimation, and collaborating on architecture for AI systems.

The Physical Design Engineer will implement AI acceleration SoCs, focusing on RTL-to-GDSII flows, synthesis, timing analysis, and collaboration with internal and external teams.

Develop and execute test automation for AI/ML software releases, troubleshoot issues, collaborate across teams, and maintain QA infrastructure.

The Design Verification Engineer will enhance verification environments for AI SoCs, collaborate on infrastructure, and automate tool flows for verification.

Lead PCIe IP/subsystem and SoC verification: develop SystemVerilog/UVM environments, create constrained-random and directed tests, verify LTSSM, link training, config space, DLL/TLP/PHY interactions, advanced PCIe features, and compliance using PCIe VIP. Build coverage, assertions, scoreboards, debug RTL/UVM, run gate-level simulations, support post-silicon bring-up, and collaborate with RTL, firmware, physical design, DFT, and validation teams.

Lead global product marketing strategy and go-to-market for EdgeCortix's AI hardware and software platforms. Shape category positioning, drive product launches, competitive intelligence, partner messaging, and cross-functional alignment while building a global product marketing team and representing the company to customers, partners, analysts, and media.

Lead UCIe IP and SoC verification by developing reusable SystemVerilog/UVM environments, protocol compliance tests, assertions, coverage models, and debug flows. Drive verification closure across subsystem and SoC integration, support gate-level and emulator-based validation, and collaborate with RTL, firmware, physical design, and post-silicon teams during bring-up.