Collaborate with engineers to extend compiler/toolchain for high-performance ML model deployment on AI hardware. Requires significant software engineering experience and knowledge of ML.

You will develop and optimize machine learning models for EdgeCortix's hardware, collaborating with engineers to meet AI performance goals.

This is an internship opportunity where candidates can submit their CV for consideration. Internships can be conducted on-site in Tokyo or India.

This role involves driving sales and business development for AI engineering solutions, building relationships, managing customer expectations, and collaborating with cross-functional teams to meet KPIs.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.

Responsible for ASIC implementation tasks including synthesis, timing constraints, ECOs, validation, and supporting RTL development and physical design activities.

Own the integration of IP into ASSP/SOC, including RTL design, synthesis, timing analysis, and verification infrastructure development. Requires expertise in Verilog and C/C++.

Design and verify ASIC chips by implementing RTL, handling synthesis, power estimation, and collaborating on architecture for AI systems.

The Physical Design Engineer will implement AI acceleration SoCs, focusing on RTL-to-GDSII flows, synthesis, timing analysis, and collaboration with internal and external teams.

Develop and execute test automation for AI/ML software releases, troubleshoot issues, collaborate across teams, and maintain QA infrastructure.

Design and verify ASIC hardware, optimize designs for power and performance, collaborate on architectural decisions, and support integration activities.

Responsible for setting up and maintaining server infrastructure and networks, providing user IT support, and ensuring security management.

The AI Application Developer will integrate AI models into web applications, manage full-stack development, and ensure performance optimization while collaborating with ML engineers.