Teams at Edgecortix

Lead SoC RTL design, integration, implementation, and quality checks across frontend, DFT, verification, and physical design. Own PPA, constraints, clocking, boot, low-power architecture, interfaces, memory subsystems, and chip-level integration. Collaborate with global architecture and engineering teams, mentor engineers, evaluate IPs, support production-quality silicon, and influence technical strategy. The role requires leadership in SoC design and verification, advanced connectivity and processor architectures, and expertise in lint, CDC, RDC, power-aware design, chiplets, and die-to-die technologies.

This internship opportunity allows candidates to gain experience in an on-site environment, specifically at the Tokyo or India office, under a flexible schedule.

Lead end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and IP blocks. Drive PPA optimization, synthesis, floorplanning, placement, CTS, routing, STA, power planning (UPF), timing closure and sign-off using Synopsys/Cadence tools. Define methodologies, collaborate cross-functionally, coordinate external implementation partners, and mentor junior engineers to ensure high-quality tape-outs and continuous process improvements.