Jobs at d-Matrix

Leads full-cycle PCB layout for complex AI accelerator cards and system baseboards. Owns high-speed routing, constraint management, stack-up definition, power delivery layouts, and design methodology. Develops SKILL, Python, or TCL automation for layout audits and reporting, and partners with power, ASIC, fabrication, and manufacturing teams to ensure DFM, DFT, DFA, and high-yield production. Requires expertise in high-density, high-speed PCB design, including 112G/224G SerDes, DDR5/HBM, HDI, and advanced materials.

Analyze emerging AI workloads and build analytical performance models and architecture simulators for current and future AI inference accelerator hardware. Collaborate with hardware, compiler, inference server, kernel, and product teams to validate assumptions, identify HW/SW optimization opportunities, incorporate architecture research, and document methodologies. The role is a hands-on technical contributor focused on performance analysis across the hardware/software boundary.

The Principal Technical Program Manager will lead engineering excellence, implement agile practices, and manage software program delivery at scale while liaising between software teams and leadership.

Design analog-mixed signal integrated circuits, optimize for low power performance, and collaborate on silicon bring up and debugging.

Develop, enhance, and maintain software kernels for AI hardware. Collaborate with teams to optimize hardware-software co-design and build compiler infrastructure.

Responsible for architecture, development, and validation of firmware/software for AI inference on multiprocessor SoCs, ensuring runtime performance. Collaborate with hardware teams and deliver quality code.

Lead end-to-end LLM inference engineering: prototype and deploy optimized inference systems across heterogeneous hardware. Build POCs, implement custom kernels and operator optimizations, drive quantization, sparsity, and batching strategies, maintain runtimes and serving frameworks, and contribute to distributed inference and performance profiling while collaborating with hardware, product, and business teams.

Lead full life-cycle technical recruiting for hardware and software roles, source deep-tech talent, manage candidates through the interview process, build ATS reporting and dashboards, partner strategically with hiring managers, and drive adoption of AI-powered sourcing and screening tools.

The Senior Staff Signal Integrity Engineer drives SI/PI strategy for AI accelerators, leads modeling/simulation, optimizes power delivery networks, and provides technical mentorship.

Responsible for defining qualification strategies for AI compute platforms, ensuring hardware reliability through testing, failure analysis, and collaboration across teams.

Responsible for demand and supply planning for server systems, managing partner contracts, and ensuring inventory and customer order fulfillment through cross-functional collaboration.

Responsible for power estimation, architectural tool development for AI workloads, and optimizing performance monitoring in micro-architecture and RTL. Collaborate with teams for design integration and silicon validation.

As a Compiler Architect, you'll design and implement a scalable MLIR-based compiler for cloud-based AI inference, focusing on optimizing large-scale AI models and architecting efficient software pipelines for deployment.

As a Principal Software Engineer, you will develop and maintain software kernels for AI hardware, collaborating on full-stack optimization and compiler infrastructure.

Own transistor-level analog design for SerDes clocking, including PLLs, DLLs, phase interpolators, clock distribution, and CDR loops. Model loop dynamics, jitter, and phase noise; develop verification environments; drive advanced-node layout; provide behavioral models; and lead silicon bring-up and bench characterization. Collaborate with datapath, DSP, digital, and firmware teams to close timing, jitter, and calibration requirements across the SerDes macro.

Lead SoC architecture definition and delivery for AI accelerators. Analyze AI workloads, drive hardware/software co-design, performance modeling, simulation tools, kernel and networking fabric work, port and optimize customer workloads, and collaborate across RTL, DV, and software teams.

Design and implement efficient algorithms to optimize LLM inference on DNN accelerators. Collaborate with mathematicians, ML researchers, and engineers to apply advanced algorithmic and numerical techniques for high-impact generative AI performance improvements.

The Principal Architect will analyze ML workloads, contribute to hardware/software features for inference accelerators, and develop analytical performance models.

Own full-cycle technical recruiting for engineering roles onsite in Bangalore for a 6-12 month contract. Source, screen, and manage candidate pipelines; partner with hiring managers on role definitions and interviews; maintain ATS data hygiene (Ashby) and deliver timely candidate communication and reporting.

Contract SRE to build, operate, and automate colo, on‑prem GPU clusters, and cloud infrastructure. Own provisioning, IaC (Terraform/Ansible), observability (Prometheus/Grafana or DataDog), incident response, runbooks, and customer-facing platform reliability.