Teams at d-Matrix

Leads full-cycle PCB layout for complex AI accelerator cards and system baseboards. Owns high-speed routing, constraint management, stack-up definition, power delivery layouts, and design methodology. Develops SKILL, Python, or TCL automation for layout audits and reporting, and partners with power, ASIC, fabrication, and manufacturing teams to ensure DFM, DFT, DFA, and high-yield production. Requires expertise in high-density, high-speed PCB design, including 112G/224G SerDes, DDR5/HBM, HDI, and advanced materials.

Analyze emerging AI workloads and build analytical performance models and architecture simulators for current and future AI inference accelerator hardware. Collaborate with hardware, compiler, inference server, kernel, and product teams to validate assumptions, identify HW/SW optimization opportunities, incorporate architecture research, and document methodologies. The role is a hands-on technical contributor focused on performance analysis across the hardware/software boundary.

The Principal Technical Program Manager will lead engineering excellence, implement agile practices, and manage software program delivery at scale while liaising between software teams and leadership.