Jobs at Credo

Owns global server infrastructure operations, reliability, security, monitoring, automation, storage, backup, identity, and cloud compute. Provides advanced Tier 2-3 troubleshooting across systems, networks, and security; resolves complex incidents; performs root-cause analysis; leads migrations, upgrades, disaster-recovery testing, and infrastructure projects; automates recurring operations; maintains security baselines and compliance controls; and coordinates with cross-functional technical teams.

Manages engineering laboratory operations, vendors, budgets, equipment maintenance, calibrations, repairs, upgrades, inventory, and technical facility procedures. Establishes ESD, safety, documentation, and security standards; oversees technicians and support staff; evaluates equipment and process issues; and coordinates lab resources with engineering, validation, systems, and IT teams to improve uptime, throughput, compliance, and cost efficiency.

Develop Python and C automation scripts and SerDes algorithms for post-silicon verification and validation of high-speed Ethernet products. Evaluate chip performance across environments, operate high-speed test equipment, analyze and debug systems, and generate test reports. Collaborate with design, firmware, and production teams on stable firmware, SLT testing, high-volume sample testing, and customer chip and IP evaluations.

Leads the company-wide Quality Management System across product development, engineering, manufacturing, suppliers, and customer support. Establishes quality policies, audits, controls, inspection plans, and performance metrics while ensuring ISO 9001 compliance. Drives risk assessment, validation, root-cause investigations, CAPA, supplier quality, customer issue resolution, and continuous improvement. Builds and mentors the Quality organization and promotes a company-wide quality culture.

Lead digital ASIC design and architecture for high-performance network interface IP supporting AI and HPC systems. Responsibilities include RTL development, architecture and roadmap definition, technical tradeoff analysis, design planning, verification partnership, synthesis, timing closure, debugging, documentation, and cross-functional technical leadership. The role requires expertise in networking standards, chip interconnects, high-speed low-power design, and semiconductor implementation.

Design and implement synthesizable RTL for high-speed SerDes PHY DSP blocks, including equalization and clock-data recovery functions. Define microarchitecture, translate DSP algorithms into RTL, optimize for power, performance, area, and latency, and verify designs. Support ASIC implementation, timing closure, CDC/RDC, DFT integration, silicon bring-up, PHY integration, and system-level debugging.

Build and ship internal applications and workflow automations from end to end. Map business processes, integrate enterprise systems, model data, develop backend and frontend functionality, and maintain production tools. Apply and evaluate LLM-powered workflows, define automation requirements, and manage build-versus-buy decisions. Partner with sales, operations, finance, product, procurement, IT, and executives while driving user adoption through training, documentation, and support.

Lead and improve the Secure SDLC across software, firmware, cloud, and AI-enabled environments. Conduct application and architecture reviews, threat modeling, source code assessments, vulnerability management, and penetration testing support. Define secure coding standards and security gates, implement DevSecOps controls including SAST, DAST, SCA, secrets scanning, and container security, and automate security testing. Partner with engineering and DevOps teams, mentor developers, and drive security-by-design practices.

The Senior Staff Accountant researches complex U.S. GAAP issues, prepares technical accounting memos, and supports SEC filings including 10-K, 10-Q, and 8-K reports. Responsibilities include coordinating close and reporting processes, preparing disclosures and XBRL tagging, supporting audits and SOX controls, monitoring regulatory developments, advising business units, and improving accounting and reporting processes through automation.

Lead system-level architecture for connecting XPUs to memory and interconnect fabrics across node, rack, and cluster scales. Define topology and communication strategies for distributed LLM training and inference, resolve integration issues across silicon, networking, memory, and software teams, and mentor system-interconnection architects. The role requires substantial NPU architecture, ASIC tapeout, silicon bring-up, validation, and production deployment experience.

Develop and execute verification plans for complex digital designs. Build reusable SystemVerilog-UVM testbenches, sequences, assertions, checkers, and coverage models. Verify PCIe and other interfaces at block and subsystem levels, conduct gate-level and firmware-based simulations, and automate verification flows with scripting. Debug silicon failures, analyze coverage gaps, and collaborate with RTL, firmware, application engineering, and architecture teams to resolve issues and improve specifications.

Leads digital design verification for high-performance networking and interface IP. Architects reusable UVM environments, develops verification plans, testbenches, assertions, coverage models, and constrained-random stimulus. Owns regressions, debugging, coverage closure, and verification sign-off while partnering with design, architecture, firmware, emulation, and post-silicon teams. Develops automation, reviews microarchitecture, mentors engineers, supports product issues, and evaluates AI-enhanced verification methods.

Own the architecture, configuration, integrations, data governance, automation roadmap, and lifecycle of the global people technology platform. Lead HR systems implementations, cross-functional integrations, self-service workflows, ticketing infrastructure, AI tool adoption, and responsible AI governance. Partner with People, IT, Finance, and Legal to improve employee experiences, reduce manual work, and deliver scalable, reliable people operations capabilities.

Manages semiconductor production execution across silicon fabs, wafer-level testing facilities, and dicing vendors. Tracks WIP, wafer lots, material movements, cycle times, testing schedules, and vendor progress. Maintains production and inventory data accuracy in ERP systems, coordinates the master production schedule, supports ship-date commitments with sales and planning data, and serves as the operational contact for external manufacturing partners.

Develop and test high-speed SerDes technologies and mixed-signal systems. Responsibilities include creating Python automation, debugging products onsite, developing test plans, characterizing SerDes performance, implementing training algorithms across copper and optical channels, collaborating with design teams, and creating customer-facing technical documentation and reference designs.

Own commercial operations for hyperscaler accounts, including customer portals, forecasts, purchase orders, fulfillment, RMAs, backlog, and invoicing. Coordinate with sales, supply chain, manufacturing, logistics, finance, and customers to resolve issues and align demand with capacity. Manage compliance, pricing, audit documentation, KPI reporting, dashboards, and process automation through EDI or API integrations. Serve as the customer’s internal advocate and support design-win tracking and new product introduction readiness.

Develop and validate high-speed SerDes DSP products by building data-capture, automated-testing, experiment-design, and analysis tools. Diagnose system-level issues across firmware, hardware, DSP algorithms, and software; improve reliability through test plans and statistical methods. Collaborate with application engineering, FAE, firmware, and design teams, present findings, and mentor colleagues.

Validate, debug, and characterize high-speed optical modules at 212.5 Gbps and beyond. Lead PCB design reviews, signal and power integrity analysis, optical system integration, testing, and production readiness. Collaborate with electrical, optical, mechanical, firmware, packaging, manufacturing, and supplier teams to resolve performance issues and advance optical transceiver products through prototype, NPI, and mass production.

Validates and optimizes high-speed optical modules and components for AI, cloud, and data-center applications. Designs optical and electrical schematics, develops and executes validation and verification test plans, performs optical and electrical measurements, analyzes performance data, and evaluates lasers, modulators, and receivers. Conducts failure analysis and collaborates with signal integrity, thermal, mechanical, firmware, manufacturing, field applications, and other cross-functional teams.

Develop PILOT software that captures hardware data, integrates local and cloud data pipelines, and produces rigorous reliability insights. Build visualizations, analyze real-world data, document tools and findings, and collaborate with optical engineers, firmware engineers, and data center operators to define meaningful performance metrics and improve products and customer operations.