Jobs at Credo

Design and verify complex front-end ASIC logic, integrate internal and external IP, and support lint, CDC, synthesis, DFT, ECO, simulation, and timing closure. Develop testbenches, participate in code reviews, and collaborate with verification, physical design, software, firmware, and systems teams through tape-out, chip bring-up, validation, and debug.

Leads digital ASIC design and architecture for high-performance network interface IP supporting AI and HPC systems. Responsibilities include RTL development, architecture and roadmap definition, RFQ evaluations, synthesis, timing closure, debugging, design reviews, technical documentation, and cross-functional stakeholder alignment. The role requires expertise in networking standards, chip interconnects, memory subsystems, low-power design, and verification collaboration.

Designs and verifies complex digital ASIC logic blocks from microarchitecture through tape-out. Responsibilities include RTL design, IP integration, functional and gate-level verification, testbench development, synthesis, timing analysis, lint, CDC, ECO support, and collaboration with physical design, DFT, software, firmware, and systems teams. The role also supports chip bring-up, feature validation, debugging, and successful product delivery.

Designs system-level memory and interconnect architectures connecting XPUs across nodes, racks, and clusters for efficient large-scale LLM training and inference. The role addresses communication bottlenecks, network topology, workload mapping, and interconnect fabric requirements while collaborating with silicon, memory, networking, compiler, software, SoC, and backend teams. Candidates should bring hands-on NPU architecture experience, including silicon definition, bring-up, validation, and production deployment.

Owns day-to-day US and Canada payroll operations, including EOR payroll processing, review, reconciliation, compliance, audits, and employee support. Leads or supports payroll system implementations, process improvements, M&A integrations, documentation, and global payroll initiatives. Partners with Finance, HR, People teams, and global stakeholders while identifying opportunities to apply AI-enabled tools. The role requires advanced Excel skills, strong North American payroll knowledge, and clear communication.

Supports end-to-end biweekly US and Canada payroll processing, including off-cycle payrolls, reconciliation, reporting, compliance, documentation, and employee inquiries. Maintains payroll records and procedures, supports audit-ready practices, contributes to process improvements and automation, and assists with special projects. The role requires knowledge of US payroll regulations, familiarity with Canada payroll, equity compensation tax treatment, and strong Excel skills.

Develops and validates high-speed optical transceiver components and subsystems. Responsibilities include precision optical alignment, fiber coupling, optical and electrical testing, test-station development, measurement automation, data analysis, troubleshooting, root-cause investigations, and technical reporting. Collaborates across optical, electrical, mechanical, and manufacturing engineering teams to support product qualification, reliability, yield, and process improvements while following laser safety and laboratory procedures.

Supports the Technology organization by translating business priorities into workforce, talent, leadership, and organizational actions. Coaches leaders, leads workforce planning, talent reviews, performance cycles, succession planning, organizational design, and change initiatives. Uses workforce data to recommend actions, coordinates with People specialists and global partners, and manages confidential plans, milestones, risks, and decision tools through completion.

Handle employee relations cases from intake through documented closure, including fact-gathering, interviews, objective summaries, escalation of significant risks, and proposed resolutions. Partner with leaders on performance improvement plans, coaching documentation, and respectful performance conversations. Maintain confidential case and PIP records, track deadlines and approvals, prepare biweekly review materials, and improve case-management tools.

Partners with Sales, Marketing, Finance, and corporate leaders to develop people plans, coach managers, support workforce and hiring planning, lead talent and performance processes, advise on organization design and change, and translate workforce insights into practical actions. Coordinates with People, Talent Acquisition, Total Rewards, Employee Relations, and Legal teams while managing confidential plans, risks, and execution milestones.

Leads the strategy, roadmap, implementation, governance, and operational management of the organization’s finance technology ecosystem. Owns NetSuite ERP and related finance applications, ensuring secure, scalable, accurate, and compliant systems. Partners with Finance, Supply Chain, Sales, and IT leaders to translate business goals into technology initiatives, drive digital transformation, improve processes, and support executive decision-making. Leads and develops a high-performing finance applications team.

Supports direct and indirect tax activities, including tax compliance, transfer pricing, intercompany settlements, tax provisions, audits, and foreign reporting. Coordinates corporate tax returns with external vendors, manages tax advisors, reviews workpapers, tracks deadlines, and supports technical analyses such as R&D credits and Section 382 studies. Partners with Accounting, FP&A, Legal, Treasury, and global tax teams while improving tax processes through AI and automation.

The Senior Finance Manager leads FP&A for product lines, managing forecasts, budgets, variance analysis, P&L support, product cost and gross margin modeling, ROI analysis, financial reporting, long-range planning, and portfolio optimization. The role partners cross-functionally with product, sales, operations, engineering, and finance teams to improve reporting, capital efficiency, and business performance.

Owns global server infrastructure operations, reliability, security, monitoring, automation, storage, backup, identity, and cloud compute. Provides advanced Tier 2-3 troubleshooting across systems, networks, and security; resolves complex incidents; performs root-cause analysis; leads migrations, upgrades, disaster-recovery testing, and infrastructure projects; automates recurring operations; maintains security baselines and compliance controls; and coordinates with cross-functional technical teams.

Design and implement synthesizable RTL for high-speed SerDes PHY DSP blocks, including equalization and clock-data recovery functions. Define microarchitecture, translate DSP algorithms into RTL, optimize for power, performance, area, and latency, and verify designs. Support ASIC implementation, timing closure, CDC/RDC, DFT integration, silicon bring-up, PHY integration, and system-level debugging.

Build and ship internal applications and workflow automations from end to end. Map business processes, integrate enterprise systems, model data, develop backend and frontend functionality, and maintain production tools. Apply and evaluate LLM-powered workflows, define automation requirements, and manage build-versus-buy decisions. Partner with sales, operations, finance, product, procurement, IT, and executives while driving user adoption through training, documentation, and support.

The Senior Staff Accountant researches complex U.S. GAAP issues, prepares technical accounting memos, and supports SEC filings including 10-K, 10-Q, and 8-K reports. Responsibilities include coordinating close and reporting processes, preparing disclosures and XBRL tagging, supporting audits and SOX controls, monitoring regulatory developments, advising business units, and improving accounting and reporting processes through automation.

Develop and execute verification plans for complex digital designs. Build reusable SystemVerilog-UVM testbenches, sequences, assertions, checkers, and coverage models. Verify PCIe and other interfaces at block and subsystem levels, conduct gate-level and firmware-based simulations, and automate verification flows with scripting. Debug silicon failures, analyze coverage gaps, and collaborate with RTL, firmware, application engineering, and architecture teams to resolve issues and improve specifications.

Leads digital design verification for high-performance networking and interface IP. Architects reusable UVM environments, develops verification plans, testbenches, assertions, coverage models, and constrained-random stimulus. Owns regressions, debugging, coverage closure, and verification sign-off while partnering with design, architecture, firmware, emulation, and post-silicon teams. Develops automation, reviews microarchitecture, mentors engineers, supports product issues, and evaluates AI-enhanced verification methods.

Manages semiconductor production execution across silicon fabs, wafer-level testing facilities, and dicing vendors. Tracks WIP, wafer lots, material movements, cycle times, testing schedules, and vendor progress. Maintains production and inventory data accuracy in ERP systems, coordinates the master production schedule, supports ship-date commitments with sales and planning data, and serves as the operational contact for external manufacturing partners.