Teams at Credo

Design and verify complex front-end ASIC logic, integrate internal and external IP, and support lint, CDC, synthesis, DFT, ECO, simulation, and timing closure. Develop testbenches, participate in code reviews, and collaborate with verification, physical design, software, firmware, and systems teams through tape-out, chip bring-up, validation, and debug.

Leads digital ASIC design and architecture for high-performance network interface IP supporting AI and HPC systems. Responsibilities include RTL development, architecture and roadmap definition, RFQ evaluations, synthesis, timing closure, debugging, design reviews, technical documentation, and cross-functional stakeholder alignment. The role requires expertise in networking standards, chip interconnects, memory subsystems, low-power design, and verification collaboration.

Designs and verifies complex digital ASIC logic blocks from microarchitecture through tape-out. Responsibilities include RTL design, IP integration, functional and gate-level verification, testbench development, synthesis, timing analysis, lint, CDC, ECO support, and collaboration with physical design, DFT, software, firmware, and systems teams. The role also supports chip bring-up, feature validation, debugging, and successful product delivery.