Jobs at Cirrus Logic

Support formal verification methodology development for digital designs. Create test plans and verification environments, formally verify microarchitecture and designs, analyze failures and coverage, and improve functional and formal verification processes. The internship requires SystemVerilog, scripting, UVM or equivalent methodologies, SVA, property-based model checking, and digital or analog design fundamentals.

Leads emerging technology ventures as an internal founder, owning opportunity discovery, technical and commercial strategy, prototyping, validation, partnerships, funding, and transition toward scalable business units. Explores technologies spanning Physical AI, edge computing, sensing, power infrastructure, robotics, and control systems. Mobilizes multidisciplinary teams, customers, startups, investors, and external partners while developing investment cases and communicating recommendations to senior leadership.

Develop and verify DFT features for mixed-signal SoCs, including Memory BIST, scan insertion, ATPG pattern generation, timing constraints, equivalence checking, and gate-level simulation. Improve test coverage, analyze test costs, deliver patterns to product test teams, and support silicon bring-up on ATE. Collaborate on DFT planning, implementation, reviews, automation, and debugging of silicon issues.

Graduate systems engineering intern supporting power electronics, motor control, system modeling, simulation, hardware prototyping, laboratory testing, and simulation-to-hardware validation. The role uses MATLAB, Simulink, Python, and laboratory instrumentation to analyze and prototype intelligent physical systems, with opportunities to apply machine learning to engineering problems. Responsibilities also include technical research, cross-functional collaboration, external partner engagement, customer discussions, and technical communication.

Design and verify high-performance analog and mixed-signal CMOS IC layouts using Cadence Virtuoso XL and Mentor Calibre. Collaborate with circuit and design engineers on device matching, signal conditioning, routing, layout planning, circuit performance, and block- and chip-level integration. The role also involves resolving layout issues and applying assisted or automated routing tools.

Software engineering interns will contribute to industrial projects in embedded firmware, software tools, software drivers, or system testing. Responsibilities may include developing C/C++, Python, Java, or Linux-based software; creating device drivers and developer tools; collaborating with hardware and UX teams; and designing automated tests for embedded hardware from FPGA emulation through silicon. Interns receive mentoring while developing technical, teamwork, planning, and problem-solving skills.

Performs teardown and competitive analysis of electronic products, reverse engineering systems, subsystems, and ICs. Develops experiments, collects measurement data, evaluates hardware, firmware, software, algorithms, and protocols, and documents architectures, schematics, component costs, and competitor capabilities. Collaborates with technical teams, develops analytical equipment and methods, produces reports and databases, monitors electronics technology, and manages competing priorities independently.

Design, build, deploy, and maintain AI-enabled applications and automation tools that improve engineering workflows. Develop LLM assistants, AI agents, document intelligence, developer productivity utilities, and enterprise integrations. Establish evaluation, monitoring, security, privacy, access-control, and responsible AI practices. Collaborate with engineering, security, IT, governance, and business teams to move AI prototypes into reliable production solutions.

Engineering internship for MEng and BEng students working on mixed-signal IC projects in analog and digital design, verification, emulation, IC layout, EMC, applications, validation, or product test engineering. Interns develop designs, perform laboratory and silicon validation, create test plans and boards, write automation scripts, analyze performance, and troubleshoot hardware. Positions are based in Edinburgh or Newbury and require full-time availability, commuting or relocation, and U.S. export-control eligibility.

Design and develop digital subsystems and DSP intellectual property for mixed-signal SoCs, from architecture and RTL through tape-out. Responsibilities include subsystem integration, complex state-machine design and verification, clock and reset domain crossing, synthesis, timing constraints, and post-silicon validation, characterization, and product testing. The role supports high-performance ICs incorporating ARM MCUs, serial interfaces, ADCs, and DACs.

Design and characterize high-performance mixed-signal integrated circuits in CMOS processes. Responsibilities include assisting with circuit design, simulation, verification, silicon prototype testing, performance analysis, and design improvements while collaborating with experienced engineering teams. The internship is full-time for 12–16 weeks and requires in-office participation, potentially up to five days per week.

Intern develops and executes pre- and post-silicon test plans for embedded software products. Responsibilities include enhancing test frameworks, debugging and triaging issues, managing defects, presenting test results, and analyzing test data to improve product quality. The role requires collaboration with experienced engineers and familiarity with embedded systems, RTOS, programming languages, software testing, version control, Jira, and continuous integration.

Support product test engineering for high-volume mixed-signal semiconductors. Responsibilities include electrical bench testing, ATE analysis, test hardware development, performance and yield data analysis, yield improvement, cost reduction, NPI activities, statistical analysis, hardware buy-off, and production ramp coordination with cross-functional teams.

Supports mixed-signal product verification through planning, testbench development, failure analysis, coverage analysis, test generation, modeling, and verification-flow development. Collaborates with digital and analog designers, applications engineers, and manufacturing test teams across pre-silicon verification and post-silicon validation.

Design and implement Verilog RTL modules for mixed-signal ICs, including DSP and data conversion circuits. Perform simulation, functional verification, synthesis, system integration, behavioral modeling, test-vector generation, and lab test development. The internship is full-time for 12–16 weeks and requires collaboration in an in-office environment.

Support mixed-signal audio hardware development through reference designs, schematic and layout coordination, circuit evaluation, bench data collection, technical documentation, firmware and RTL implementation, and Python or C scripting for automated analysis. The internship requires an Electrical Engineering bachelor’s student with analog, digital, and mixed-signal circuit knowledge, programming experience, and familiarity with laboratory measurement equipment.

Design and verify high-performance analog and mixed-signal CMOS integrated circuit layouts using Cadence Virtuoso XL and Mentor Calibre. Collaborate with circuit and design engineers on layout planning, device matching, signal conditioning, routing, integration, and resolving layout issues to optimize circuit performance.

Designs and completes analog and mixed-signal IC layouts, including floor planning, block and chip-level routing, device matching, digital-analog integration, and physical verification. Troubleshoots LVS issues, applies design-for-manufacturing and reliability techniques, estimates layout schedules, resolves design problems, and collaborates with design and physical engineering teams using CAD tools and foundry PDKs.

Design and develop digital IC architectures, RTL, and block-level testbenches for complex mixed-signal SoCs. Responsibilities include design integration, verification, synthesis, timing analysis, technical reviews, IP quality, and mentoring junior engineers. The role collaborates with mixed-signal, DFT, place-and-route, and validation teams through production and chip bring-up.

Designs and verifies high-performance analog and mixed-signal CMOS IC layouts using Cadence Virtuoso XL and Mentor Calibre. Responsibilities include floor planning, block and top-level routing, device matching, shielding, isolation, ESD-aware layout, LVS debugging, and resolving design issues in collaboration with circuit and design engineers. The role requires strong knowledge of analog layout techniques, semiconductor reliability effects, foundry PDKs, and layout automation.