Jobs at Cirrus Logic

The CAD Engineer role focuses on developing the automation foundation for silk design teams, enhancing EDA tools, and improving workflows across the organization.

Lead Cirrus Logic's federal and Texas government affairs and regulatory strategy. Advocate before Congress, agencies, and trade associations on export controls, trade, immigration, and semiconductor policy; translate regulatory and geopolitical developments into business risk and opportunity assessments; manage outside lobbyists and coalition engagement; support regulatory strategy and coordinate with Legal, Investor Relations, and executive leadership. Maintain relationships with policymakers, represent the company at industry forums, and ensure policy positions protect supply chain, market access, and talent.

Design and verify analog and mixed-signal IC layouts. Collaborate with engineers, create floorplans, and contribute to IC development projects.

Design, simulate, and validate advanced I/O and ESD protection structures for mixed‑signal CMOS chips. Own I/O library release and modeling, drive chip‑ and block‑level ESD sign‑off, define ESD/latch‑up methodology, collaborate with foundries, and lead cross‑team reliability and layout guidance.

Lead global engineering IT infrastructure supporting 1,000+ semiconductor design engineers. Own strategy, availability, performance, security, and scalability of Linux platforms, HPC/compute farms, enterprise storage, revision control, automation, observability, incident response, capacity planning, and cross-functional alignment to improve engineering productivity and tapeout reliability.

The role involves developing technology concepts, designing transistor-level circuits, performing silicon validation, and analyzing data to drive innovation in IC design.

The Senior Analog Design Engineer will develop mixed-signal IC designs, oversee project phases, conduct lab tests, and lead design for power management applications.

Lead the Silicon NPI team to bridge foundry process capabilities and mixed-signal design, resolve SOA/DRC/reliability issues, drive foundry engagement, improve yield and cost, and develop engineering staff.

Lead planning, execution, and optimization of multi-channel marketing campaigns (digital, social, events, PR, partner). Drive campaign strategy, content and multimedia, partner co-marketing, demand generation, analytics, and sales enablement to increase brand visibility and pipeline.

The role involves designing analog and mixed-signal IC layouts, solving layout issues, collaborating with design engineers, and improving layout processes.

Design, simulate, and validate advanced I/O and ESD protection circuits. Develop silicon test structures for ESD and latch‑up evaluation, translate silicon data into design rules, release and maintain I/O libraries and models, drive chip‑ and block‑level ESD sign‑off, and lead cross‑team ESD and I/O reliability strategy.

Design and verify DFT features for mixed-signal SoCs: insert and verify Memory BIST and scan, generate ATPG patterns, perform gate-level verification, analyze test coverage and costs, and deliver patterns/support silicon bringup on ATE.

The Embedded Software Engineer will customize device drivers for Windows and Linux, integrate audio processing and DSP, and support customer issues.

The Executive Administrative Assistant will support R&D leadership through calendar management, meeting coordination, travel logistics, and special projects to enhance the efficiency of the engineering organization.

The Hardware Applications Engineer will lead customer design, system integration, PCB reviews, and training, ensuring optimal audio product performance and adoption.

The role involves designing mixed-signal layouts, collaborating with design engineers, solving layout issues, and utilizing techniques for efficient circuit performance.

As a Physical Design Engineer, you'll implement complex mixed-signal SoCs, optimizing timing and collaborating within a design team, while also developing design methodologies.

Design and verify high-performance mixed-signal CMOS IC layouts, collaborating with engineers on optimization, layout techniques, and troubleshooting.

Responsible for developing low-power, high-performance ICs in advanced CMOS processes, including design, validation, and post-silicon activities.

Responsible for defining and implementing DFT strategies for ASICs, collaborating with teams, and improving DFT productivity through automation.