Teams at Cirrus Logic

Support formal verification methodology development for digital designs. Create test plans and verification environments, formally verify microarchitecture and designs, analyze failures and coverage, and improve functional and formal verification processes. The internship requires SystemVerilog, scripting, UVM or equivalent methodologies, SVA, property-based model checking, and digital or analog design fundamentals.

Leads emerging technology ventures as an internal founder, owning opportunity discovery, technical and commercial strategy, prototyping, validation, partnerships, funding, and transition toward scalable business units. Explores technologies spanning Physical AI, edge computing, sensing, power infrastructure, robotics, and control systems. Mobilizes multidisciplinary teams, customers, startups, investors, and external partners while developing investment cases and communicating recommendations to senior leadership.

Develop and verify DFT features for mixed-signal SoCs, including Memory BIST, scan insertion, ATPG pattern generation, timing constraints, equivalence checking, and gate-level simulation. Improve test coverage, analyze test costs, deliver patterns to product test teams, and support silicon bring-up on ATE. Collaborate on DFT planning, implementation, reviews, automation, and debugging of silicon issues.