Jobs at Bitdeer Group

Responsible for leading US media strategy, brand storytelling, and public affairs in the AI and crypto-mining sector, while maintaining relationships with journalists.

Design, develop and maintain cloud platform services, focusing on distributed systems and cloud-native infrastructure. Collaborate across teams, implement observability solutions, and mentor junior engineers while enhancing organizational performance through engineering management principles.

Lead global treasury front office: FX risk management and hedging, liquidity and cash optimization, bank relationship management, trade/project financing, TMS implementation, governance, and treasury advisory across jurisdictions.

Join the Graduate Talent Trainee program focusing on IC Design and Embedded Software. Develop technical expertise and work on innovative projects at Bitdeer.

As a Senior Front-End Engineer at Bitdeer, you will implement RTL in Verilog for CPU/NPU cores, collaborate on architecture design, and assist with verification and debugging throughout development stages.

Lead a team in verifying complex IC designs, develop verification strategies, and ensure high-quality silicon through advanced methodologies and collaboration.

The Senior AI Cloud Product Manager will define and execute a cloud infrastructure and AI platform strategy, manage product roadmaps, gather user requirements, track key performance indicators, and lead product vision for AI-native offerings.

Develop and execute test plans for digital design verification, manage regressions and coverage, and collaborate with design teams to ensure design correctness.

The Senior Legal Counsel will provide legal support for capital markets transactions, compliance with SEC regulations, M&A, and corporate governance at Bitdeer.

The AI Cloud Architect will develop cloud strategies, design solutions, lead migrations, implement governance, and drive AI integration while managing relationships with service providers and ensuring security compliance.

Manage financial control for a large-scale data center, overseeing CAPEX/OPEX, budgeting, compliance with accounting regulations, and cost analysis.

The Project Coordinator will support the high-level construction of an AI Datacenter, managing schedules, documentation, vendor coordination, and communication to ensure timely project execution and compliance with Norwegian standards.

The Sales Manager is responsible for executing sales strategies, identifying new business opportunities, managing client relationships, and preparing market reports. They will collaborate with internal teams and lead promotional activities.

Provide omnichannel Tier 1 customer support via Zendesk, WhatsApp, and Telegram; troubleshoot common technical issues, route or escalate complex cases to Engineering/Technician teams, document interactions in the ticketing system, and assist with administrative or customer-success tasks as needed.

Manage end-to-end procurement for AI compute: supplier development, RFQ, negotiation, contracts, and delivery for GPU/CPU servers, EDA software, datacenter services; track market trends, control spend, mitigate cross-border and licensing risks, and report on supplier performance.

Develop and execute comprehensive, coverage-driven verification environments using SystemVerilog/UVM. Implement testbenches, run RTL simulations/emulation (Palladium/HAPS/Zebu), debug RTL, maintain regression suites, improve coverage metrics, and document verification results.

Own architecture of a 3D-DRAM memory subsystem for an NPU: design controller microarchitecture, address/bank mapping, QoS, refresh/ECC/RAS and thermal-aware throttling; specify PHY/vendor interfaces; build cycle-approximate performance models; define verification and co-verification plans; and lead vendor and cross-team integration through silicon bring-up.

Design and implement Verilog RTL for SoC blocks, integrate IPs, and support synthesis, timing closure, power optimization, and floorplanning. Contribute to design verification and emulation, assist with pre- and post-silicon debugging, and automate design tasks with scripting.

Design and implement Verilog RTL for PCIe-related IP blocks, drive verification closure and functional coverage, assist pre- and post-silicon debug, and collaborate with verification and software teams to deliver robust SoC/IP solutions.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.