Jobs at Ambarella, Inc.

Leads global channel strategy and partner-led revenue growth for Edge AI and Physical AI solutions. Builds relationships with distributors, OEMs, ODMs, solution providers, GSIs, and ecosystem partners; develops joint business plans, pipeline, commercial programs, enablement, and go-to-market motions. Coordinates cross-functional teams to commercialize Ambarella-based platforms, drive design wins and production deployments, and improve partner productivity across global markets.

Develop and execute verification solutions for advanced SoCs used in video, image processing, computer vision, and AI applications. Build SystemVerilog and UVM testbenches, create verification plans, develop directed and constrained-random tests, and implement assertions, checkers, and coverage models. Debug RTL and testbench failures, automate regression workflows with Python, enhance agentic AI verification processes, and collaborate with design, architecture, and software teams.

Lead verification for advanced SoCs containing image and video processors, DSPs, CPUs, and neural network accelerators. Own verification strategies, architect reusable SystemVerilog and UVM environments, develop tests and coverage models, debug RTL and system issues, and drive coverage closure. Improve AI-assisted verification workflows, simulation efficiency, regression automation, and failure triage. Collaborate across architecture, design, firmware, and software teams while mentoring junior engineers and providing technical leadership.

Verify complex digital logic and media processor designs by developing UVM and SystemVerilog testbenches, executing test plans, analyzing functional and code coverage, debugging SoC platforms, and creating verification tools. The role validates DSP blocks, control logic, processor cores, image-processing pipelines, video compression engines, and neural-network processors while collaborating with RTL, architecture, and software teams.

Supports physical design implementation and verification for low-power AI SoCs, working from netlist to GDSII. Responsibilities include floorplanning, automated place and route, static timing analysis, ECO implementation, signal integrity, EM/IR analysis, formal verification, and physical layout verification using LVS, DRC, and DFM at block or full-chip level.

Develop applications for embedded Linux systems, maintain SDK build systems and device drivers, and provide technical support to customers worldwide. Collaborate across teams on software development and customer documentation. The role requires strong C programming, Linux kernel and driver knowledge, embedded hardware understanding, and familiarity with build and container technologies including Yocto, Docker, Podman, Kubernetes, and K3s.

Leads development, optimization, modeling, and verification of real-time hardware video codecs for AI-enabled camera silicon. Designs embedded firmware, rate-control systems, diagnostics, and silicon validation tools while driving hardware/software co-design. Collaborates with architecture, hardware, and software teams, provides technical leadership, and mentors junior engineers.

Develop and maintain neural network compression algorithms and tools for AI vision processors used in edge applications. Apply pruning, quantization, knowledge distillation, and compression training techniques to CNN- and transformer-based computer vision and large language models. Work with machine learning frameworks and program in C, C++, and/or Python.

Design, implement, optimize, and validate autonomous driving algorithms for perception, tracking, prediction, planning, localization, and real-time map generation. Ensure sensor data formats, timing, synchronization, coordinate alignment, and fallback mechanisms meet ISO 21448 SOTIF requirements. Integrate algorithms with systems and software teams into production-grade autonomous driving stacks.

Manage domestic and international travel arrangements, calendars, billing, records, reports, office operations, space planning, facility support, events, and special projects. The role requires strong organization, communication, multitasking, attention to detail, Microsoft Office proficiency, and the ability to lift up to 20 pounds.

Leads strategic business development and sales for AI and vision SoC solutions. Owns account plans, drives customer design wins, develops new markets, manages customer and manufacturing ecosystems, negotiates pricing and contracts, and oversees forecasting and market reporting. The role engages executives, engineering teams, and purchasing leaders while collaborating with internal technical, marketing, finance, legal, and operations teams. It requires substantial semiconductor sales experience and includes 20–30% domestic travel.

Lead product marketing and go-to-market strategy for edge AI solutions serving robotics, drones, machine vision, and industrial automation markets. Define hardware and software positioning, gather customer requirements, shape roadmaps, enable sales and FAE teams, grow partner and developer ecosystems, and support Ambarella’s Developer Zone. Manage cross-functional initiatives, technical demonstrations, events, customer relationships, and partner programs, with up to 30% international travel.

Design, implement, and test imaging and video algorithms and DSP microcode for Ambarella SoCs. Develop firmware, research and implement DSP algorithms, optimize CPU and memory usage, create hardware-block test code, and debug assembly. The role requires understanding computer architecture, video standards, image processing, neural network frameworks, software development practices, and cross-functional teamwork.

Develop highly efficient deep learning and computer vision algorithms for edge applications, including self-driving cars and humanoid robots. Responsibilities include designing, training, and optimizing Transformer models, researching multimodal large language models and embodied AI, and building vision systems. The role also involves applying computer vision methods such as object detection, tracking, segmentation, and vision-language modeling, alongside robot control and sensor integration using ROS 2.

Develop software tools for future Ambarella embedded processors used in computer vision and intelligent automotive applications. Design and implement compiler language features, performance optimization tools, and related development capabilities. Collaborate with scientists, architects, and software and hardware teams to optimize chip performance. Work independently within a small R&D team.

Supports senior circuit designers in designing, validating, and characterizing mixed-signal and analog IP blocks for SoCs, including PLLs, DLLs, SERDES, high-speed I/O, and data converters. The role provides exposure to advanced sub-14nm technologies, analog integrated circuit design, digital logic, Verilog coding, laboratory work, and signal integrity.

Design and verify Design-for-Test logic for complex SoCs, automate scan, compression, and MBIST flows, analyze fault coverage, and perform timing analysis for DFT modes.

Develop and debug verification testbenches, tests, RTL logic, random test generators, coverage monitors, checkers, assertions, and simulation-analysis tools for complex SoCs featuring DSP, computer vision, CPU, and coprocessor blocks.

Design and verify ASIC logic for edge AI vision processors, including video compression, image processing, neural-network accelerators, and processor cores. Develop RTL in Verilog and SystemVerilog, optimize designs for timing, area, and power, and create UVM-based testbenches, BFMs, test generators, coverage monitors, and verification plans. Support synthesis, front-end tool flows, chip bring-up, and testing.

Implements and verifies design-for-test features, including scan, compression, MBIST, LBIST, and streaming scan networks, for complex computer vision SoCs. Develops scan and memory-test patterns, analyzes clocking for at-speed testing, performs post-layout timing verification, supports ATE pattern bring-up, and assists with silicon production, failure diagnosis, and test optimization.