Top Engineering Jobs

Lead HBM package and product engineering efforts to improve yield, quality, cost, cycle time, and scale. Drive assembly and cube yield improvements, root-cause failure analysis (EFA/PFA), process conversions, cross-functional projects, and AI/ML model deployment to optimize KPIs. Manage projects, technical decisions, and collaborate with fab, TD, design, quality, and packaging teams to deliver high-volume manufacturing HBM products.

Design and produce multi-dimensional semiconductor layouts from schematics, lead major block developments, verify data integrity, improve layout efficiency via automation, collaborate across global design and CAD teams, and deliver quality-controlled layouts on schedule.

The Staff Engineer oversees wet process module execution for NAND, optimizing processes, leading experiments, and driving cross-functional integration to enhance yield and reliability.

The Principal Engineer leads wet process development for NAND memory technology, driving experiments, cross-functional collaboration, and innovation in process solutions.

The Senior Engineer will design and validate on-chip controllers and mixed signal circuitry in NAND FLASH chips, performing RTL design, firmware coding, and full-chip verification.

Develop and maintain metrology measurement recipes and inspection strategies to detect defects and improve yield. Use advanced analytics and SPC to monitor tools, design experiments to find defect sources, collaborate with cross-functional teams and suppliers, and run projects to improve inline detection, efficiency, cost, and tool availability. Integrate AI-assisted tools and provide data-driven recommendations to support fab operations and continuous improvement.

As a Process Integration Engineer, you will conduct yield investigations, drive efficiency improvements, validate processes, and support tech transfer while collaborating with teams in a fast-paced environment.

As a Senior CAD Engineer, you will improve EDA tools, support memory layout teams, and develop methodologies for automation and reliability in layout workflows.

Technical leader for photolithography Track & Trim equipment development. Lead equipment selection, installation, qualification, and deployment (including EUV), drive uptime/reliability improvements, embed safety practices, and partner with process, manufacturing, and vendors to scale solutions across global fabs.

Provide senior architectural leadership for DRAM-related ASIC and logic solutions, driving high-bandwidth, energy-efficient, scalable, and reliable memory architectures. Lead silicon-package-system co-optimization, partitioning, interface definition, PPA and IO timing analysis, and practices to ensure first-silicon success. Mentor teams and influence cross-functional decisions to meet product and market requirements.