Top Engineering Jobs

The Lead Principal Engineer will lead advanced IC layout development, ensuring compliance with design rules and methodologies while mentoring engineers and collaborating across teams.

Develop and maintain smart scheduling systems, optimize scheduling processes, ensure project timelines are met, and collaborate with cross-functional teams.

The role involves facility hookup and system integration, collaborating with various teams for tool installation, and using BIM software for modeling and design changes.

Lead probe strategy and silicon learning from pre-silicon staging through first-silicon bring-up and HVM. Define probe coverage, limits, and guard-bands using silicon characterization. Collaborate with Design, DFT, DV, Process Integration, Backend Test, and Reliability to drive yield, quality, cost, and test-efficiency improvements. Enable NPI, perform device characterization, root-cause analysis, and apply data/AI for probe and test optimization.

Lead process integration and yield ramp for DRAM modules across tech transfer and early HVM. Drive root-cause analysis using DOE, SPC/FDC, FMEA, and 8D, ensure manufacturability and reliability, manage a team of PI engineers, coordinate cross-functional alignment, support NPI and tech-transfer activities including extended international assignments, and sustain process control and operational excellence during ramps.

Lead end-to-end IP and SoC development from micro-architecture through reusable RTL design, integration, and post-silicon bring-up. Drive CDC, lint, synthesis/STA, and power analysis; define module interfaces and system-level architecture. Collaborate with Verification, FW, DFT, Synthesis, and Physical Design teams, mentor engineers, and apply AI-enabled workflows per Micron governance to improve productivity and automation.

Develop, optimize, and qualify diffusion deposition, anneal and reflow processes in high-volume semiconductor manufacturing. Troubleshoot line issues, run equipment/material evaluations, collaborate with suppliers and fab teams, and apply structured problem-solving (FMEA, 8D, SPC) to improve yield, quality, reliability, and cost.

Design and maintain UVM-based SystemVerilog verification environments, build Python testbenches, execute block/system verification plans, debug complex integration issues, drive coverage closure, and adopt AI-assisted techniques to improve verification productivity and quality while collaborating closely with design teams.

The Principal Design Engineer leads the design and implementation of NAND datapath circuits, manages timing analysis, and mentors other engineers. Responsibilities include circuit ownership, physical design, simulation, and collaboration across teams.

Lead design, construction, testing/commissioning, and operations of semiconductor facility instrumentation and control systems (I&C/ELV/SCADA/IoT), ensure reliability and global standards, manage large greenfield projects, collaborate cross-functionally, integrate sustainability, and provide technical leadership across the full project lifecycle.