Top Engineering Jobs

Lead silicon debug and product quality for HBM products, influencing design decisions and ensuring system stability across customer platforms. Drive continuous improvement through technical leadership and cross-functional collaboration.

As a Memory Design Engineer, you will design and analyze digital and analog circuits for memory products, collaborating across teams to ensure manufacturable solutions that optimize quality and cost.

As a Software Development Engineer, you will develop, maintain, and support applications, analyze software specifications, and collaborate with various teams to implement solutions while ensuring quality and performance.

Support and optimize photo track semiconductor processes by establishing process conditions, setting equipment parameters, analyzing abnormalities, implementing improvements, and driving cost and capability upgrades to ensure efficient, safe production.

The role involves verifying full chip designs, developing test cases, and collaborating globally on advanced memory technologies. Key focus on low power designs and AI-based automation integration.

Design and implement complex analog, mixed-signal, and custom digital layout blocks for NAND Flash. Perform floorplanning, placement, routing, parasitic-aware optimization, extraction and validation. Collaborate cross-functionally to ensure manufacturability and performance. Develop automation, scripting and AI-assisted, data-driven layout methodologies and improve layout methodology and documentation.

Lead and manage spares engineering and test-wafer programs in a semiconductor fab. Drive cost, productivity, and quality improvements, optimize test wafer usage, coordinate cross-functional and cross-site stakeholders, perform benchmarking and data-driven analysis, and present status to leadership while ensuring documentation, compliance, and supplier collaboration.

Analyze inline, param, probe, and experiment data to identify and resolve wafer yield issues. Communicate findings to fab process teams, lead multi-area focus teams, publish Pareto yield limiters, support technology transfers, and integrate AI-assisted tools to improve yield and quality.

Lead cross-functional design enablement for DRAM, defining and refining design rules, test structures, APR workflows, and milestones. Coordinate with Design, Process Integration, Product Engineering, and Mask teams to optimize PPAC, evaluate test structures, resolve process/layout issues, and implement GenAI/LLM-compatible workflows for efficiency.

The role involves designing DRAM chip layouts, conducting layout verification, and collaborating globally to meet project schedules while ensuring quality standards.