The Role
Lead and manage a team in RTL design verification, defining strategies, overseeing development, debugging issues, and reporting progress.
Summary Generated by Built In
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects.
Key Responsibilities
- Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables.
- Define and execute verification strategies and plans for complex digital blocks and systems.
- Oversee the development of robust and reusable verification environments using SystemVerilog and UVM.
- Review and approve verification plans, testbenches, and coverage metrics.
- Drive functional and coverage-based verification across multiple block/system verification cycles.
- Collaborate with design engineers to debug and resolve functionality issues.
- Ensure effective resource allocation and project planning to achieve optimal results.
- Foster a culture of technical excellence, continuous learning, and innovation within the team.
- Report verification progress, issues, and risks to senior management and other stakeholders.
Required Qualifications
- 10+ years of experience in digital design verification—a must.
- 3+ years of experience managing or leading verification teams.
- Proven track record of completing two or more full block/system verification cycles.
- In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW.
- Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM).
- Experience in block, cluster and full chip verification levels.
- Strong problem-solving skills and the ability to debug complex functionality issues.
- Excellent leadership, communication, and organizational skills to manage and inspire a team.
Preferred Qualifications
- Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes.
- Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
- Familiarity with formal verification techniques and tools.
- Background in system-level verification or post-silicon validation.
- Experience with project planning tools and methodologies for effective team management.
Top Skills
Ethernet
Pcie
Perl
Python
Serdes
Systemverilog
Uvm
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The Company
What We Do
We are a semiconductor startup that has brought together a world-class team of ASIC designers, optical communications experts and seasoned investors that excel at creating disruptive technologies.
Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
