Technologist, ASIC Development Engineering - STA Architect

Posted 13 Hours Ago
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Bengaluru, Karnataka
Expert/Leader
Big Data • Cloud • Hardware • Software
The Role
The Technologist, ASIC Development Engineering - STA Architect will lead a technical team in Static Timing Analysis, focusing on the timing closure of complex ASIC designs. Responsibilities include developing methodologies, conducting timing analysis, collaborating with various teams, mentoring engineers, and resolving timing issues.
Summary Generated by Built In

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

Job Summary:

We are seeking an experienced STA Architect to lead our technical team. The ideal candidate will have extensive experience in Static Timing Analysis, a deep understanding of digital design, and the ability to lead and mentor a team of engineers.

This role requires hands-on expertise in STA tools, methodologies, and a strategic vision to drive the timing closure of complex designs.


Key Responsibilities:

- Lead the STA function and oversee all aspects of timing analysis and closure for ASIC designs.

- Develop and implement STA methodologies and best practices to ensure high-quality design closure.

- Collaborate with cross-functional teams, including IP design, DFT, and verification teams, to address timing challenges and drive design convergence.

- Conduct thorough timing analysis using industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).

- Define and drive timing constraints development and validation processes.

- Provide technical leadership and mentorship to junior engineers, fostering a culture of continuous learning and innovation.

- Work closely with project managers to ensure timely delivery of design milestones and project goals.

- Stay updated with the latest industry trends and advancements in STA methodologies and tools.

- Participate in design reviews, providing expert insights and recommendations to optimize performance and timing.

- Troubleshoot and resolve complex timing issues, utilizing advanced debugging techniques.

Qualifications

Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

- Minimum of 15 years of experience in Static Timing Analysis, with a proven track record of successful timing closure on multiple complex designs.

- In-depth knowledge of STA tools such as Synopsys PrimeTime, Cadence Tempus, or similar.

- Strong understanding of digital design principles, including RTL design, synthesis, place and route, and clock tree synthesis.

- Experience with timing constraint development and validation.

- Proficient in scripting languages (e.g., TCL, Perl, Python) for automation of STA tasks.

- Excellent problem-solving skills and the ability to troubleshoot complex timing issues.

- Strong leadership and team management skills, with experience leading and mentoring engineers.

- Effective communication skills, with the ability to articulate complex technical concepts to cross-functional teams.

- Strong organizational skills and the ability to manage multiple tasks and projects simultaneously.

- Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.

Additional Information

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Top Skills

Cadence
Synopsys
The Company
HQ: Bengaluru, Karnataka
25,132 Employees
On-site Workplace

What We Do

At Western Digital we create data storage solutions that power the technology of today and inspire the innovations of tomorrow.

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