Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Overview
Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.
Key Responsibilities
- Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
- Collaborate with verification teams to review test plans and debug issues.
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
- Scripting and automation for ASIC methodology improvement.
- Accountable for quality and overall design success with the support of senior engineers.
Required Qualifications
Education & Experience:
- Bachelor’s degree in electrical engineering or equivalent
- 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
Digital Design Expertise:
- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
- Track record of delivering high-quality digital designs from definition to production.
- Experience in high-speed design in advanced technology nodes.
- Understanding of functional and formal verification at block and chip level.
- Understanding of clocking, CDC and RDC and static-timing analysis
Protocols & Integration:
- Proficient with high-speed protocols such as PCIe, Ethernet, DDR, or similar
- Experience with IP development and integration
Tools & Methodologies:
- Expertise in design methodology, CAD automation or design infrastructure.
- Proven SystemVerilog and Python expertise in a production environment
- Familiarity with Synopsys and/or Cadence digital design flows
- Basic understanding of UVM-based verification methodologies
Professional Attributes:
- Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
- Good communication and collaboration skills; comfortable working cross-functionally with global teams
- Self-directed learner who adapts quickly to changing requirements
- Customer-focused mindset with the ability to prioritize and work independently to deliver high-quality designs.
Preferred Qualifications
- Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
- Knowledge of design-for-test (DFT) in a production environment.
Base salary range is $160,000 USD-$200,000 USD,and will be determined based on the candidate's capabilities and employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in electrical engineering or equivalent
- 5+ years of experience developing SoC or silicon products in server, storage, and/or networking markets
- Expertise in RTL coding with SystemVerilog
- Experience with synthesis using Synopsys or Cadence tools
- Track record delivering digital designs from definition through production
- Experience with high-speed design in advanced technology nodes
- Understanding of functional and formal verification at block and chip level
- Understanding of clocking, clock-domain crossing, reset-domain crossing, and static-timing analysis
- Proficiency with high-speed protocols such as PCIe, Ethernet, DDR, or similar
- Experience with IP development and integration
- Expertise in design methodology, CAD automation, or design infrastructure
- Proven SystemVerilog and Python expertise in a production environment
- Familiarity with Synopsys and/or Cadence digital design flows
- Basic understanding of UVM-based verification methodologies
- Experience with embedded firmware development or standard embedded processor subsystems such as RISC-V or Arm
- Knowledge of design-for-test in a production environment
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
-
Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
-
Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
-
Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
.png)
