Responsibilities:
Define and implement test plans and verification strategies based on design specifications and requirements (20%).
Develop assertion-based checkers and functional coverage models aligned to verification plans (20%).
Perform functional verification of RTL designs using industry-standard methodologies (e.g. UVM) (20%).
Generate and analyse coverage reports to ensure verification of completeness and quality (20%).
Collaborate with design and architecture teams to understand system requirements and ensure alignment (10%).
Identify, debug, and resolve verification issues and design bugs (10%).
Minimum Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
8+ years of experience in SoC verification.
Strong hands-on experience with UVM-based verification methodologies.
Proven experience in defining and executing test and verification plans.
Experience with coverage-driven verification and coverage analysis.
Proficiency in SystemVerilog and assertion-based verification.
Familiarity with industry-standard verification tools (e.g. VCS, QuestaSim).
Experience with IC design verification at block and SoC level.
Knowledge of formal verification techniques.
Experience verifying bus architectures (e.g. AMBA AHB/AXI, NoC, Bus Fabric) in UVM environments.
Understanding of low-power verification methodologies.
Strong analytical, debugging, and problem-solving skills.
Excellent communication and teamwork abilities.
Desired Qualifications
Strong programming skills in Python.
Experience in wireless SoC design and verification.
Knowledge of scripting languages (e.g. Tcl, Python, Perl) for automation.
Familiarity with version control systems (e.g. Git).
Skills Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in SoC verification
- Strong hands-on experience with UVM-based verification methodologies
- Experience defining and executing test and verification plans
- Experience with coverage-driven verification and coverage analysis
- Proficiency in SystemVerilog and assertion-based verification
- Familiarity with verification tools such as VCS and QuestaSim
- Experience with IC design verification at block and SoC levels
- Knowledge of formal verification techniques
- Experience verifying bus architectures such as AMBA AHB, AMBA AXI, NoC, or Bus Fabric in UVM environments
- Understanding of low-power verification methodologies
- Strong analytical, debugging, and problem-solving skills
- Excellent communication and teamwork abilities
- Strong programming skills in Python
- Experience in wireless SoC design and verification
- Knowledge of scripting languages such as Tcl, Python, or Perl for automation
- Familiarity with version control systems such as Git
Semtech Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Semtech and has not been reviewed or approved by Semtech.
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Parental & Family Support — Up to 20 weeks of paid maternity/parental leave is highlighted in multiple regions. Enhanced leave is positioned as a core part of the package.
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Healthcare Strength — Medical, dental, and vision coverage are standard elements of the offering. Core health coverage features prominently alongside other benefits.
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Leave & Time Off Breadth — Paid vacation and time‑off programs are explicitly included. Time off is emphasized together with flexible/hybrid work policies where possible.
Semtech Insights
What We Do
Semtech Corporation is a high-performance semiconductor, IoT systems and Cloud connectivity service provider dedicated to delivering high quality technology solutions that enable a smarter, more connected and sustainable planet.
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