Staff Physical Design Engineer

Posted 18 Days Ago
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Pune, Maharashtra, IND
In-Office
Senior level
Semiconductor • Manufacturing
The Role
Lead block-level physical implementation of digital blocks/IP from netlist to GDSII: floorplanning, power planning, placement, CTS, routing, STA, physical verification and sign-off, low-power implementation (UPF), flow automation, ECO support, and tape-out correlation.
Summary Generated by Built In
Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

About the Role

Lattice Semiconductor is seeking a Staff Physical Design Engineer to join our Pune engineering center. In this role, you will own physical implementation of complex digital blocks and IP for our low-power FPGA products — from netlist to GDSII — working closely with RTL design, integration, and architecture teams to deliver first-pass silicon.

Responsibilities

  • Own block-level physical design execution: floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure
  • Drive synthesis and place-and-route flows using industry-standard EDA tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, or equivalent)
  • Perform static timing analysis and closure across PVT corners and modes
  • Execute physical verification and sign-off: DRC, LVS, ERC, antenna, EM/IR analysis
  • Implement low-power design techniques — UPF-based power intent, power gating, multi-Vt optimization
  • Collaborate with RTL, DFT, and integration teams to resolve design convergence issues and support ECO cycles
  • Contribute to flow automation and methodology improvements using scripting (TCL, Python, Perl)
  • Support tape-out activities and correlate physical design metrics with post-silicon results

Requirements

  • Bachelor's or Master's degree in Electronics/Electrical Engineering or related field
  • 6+ years of hands-on physical design experience in ASIC/SoC or FPGA silicon development
  • Strong expertise in synthesis, P&R, STA, and physical sign-off on advanced process nodes
  • Working knowledge of low-power implementation (UPF/CPF) and design convergence at block and subsystem level
  • Proficiency in TCL/Python scripting for flow automation
  • Strong debugging skills and a track record of successful tape-outs
  • Excellent cross-functional communication and ownership mindset

Preferred

  • Experience with FPGA or custom silicon physical implementation
  • Exposure to EM/IR analysis tools (Ansys RedHawk/Totem) and DFM closure
  • Advanced node experience (16nm and below)

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

Skills Required

  • Bachelor's or Master's degree in Electronics/Electrical Engineering or related field
  • 6+ years hands-on physical design experience in ASIC/SoC or FPGA silicon development
  • Experience with Synopsys Fusion Compiler / ICC2 or Cadence Innovus (place-and-route tools)
  • Strong expertise in synthesis, place-and-route, static timing analysis (STA), and physical sign-off on advanced process nodes
  • Working knowledge of low-power implementation using UPF/CPF, power gating, and multi-Vt optimization
  • Proficiency in TCL and Python scripting (Perl also mentioned) for flow automation
  • Experience executing physical verification and sign-off tasks: DRC, LVS, ERC, antenna checks, EM/IR analysis
  • Strong debugging skills with a track record of successful tape-outs
  • Excellent cross-functional communication and ownership mindset
  • Experience with FPGA or custom silicon physical implementation
  • Exposure to EM/IR analysis tools (Ansys RedHawk / Totem) and DFM closure
  • Advanced node experience (16nm and below)
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The Company
HQ: Hillsboro, OR
975 Employees
Year Founded: 1983

What We Do

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world. Lattice was founded in 1983 and is headquartered in Hillsboro, Oregon with major operations in San Jose, California, Shanghai, China, and Manila, Philippines.

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