Jobs at Lattice Semiconductor

Leads global internal communications and executive storytelling, including communications strategy, intranet governance, employee engagement, executive presentations, change communications, and cross-functional messaging. Advises senior leaders, translates complex technical and business topics, manages communication measurement, supports organizational changes and milestones, and ensures materials align with brand standards. The role also evaluates AI-enabled communications tools and partners with teams across a global, matrixed organization.

Leads functional verification of complex FPGA and ASIC IPs, subsystems, and SoC features through tape-out. Develops SystemVerilog/UVM environments, test plans, assertions, scoreboards, coverage models, and regression strategies. Debugs RTL, gate-level, low-power, and system-level simulations; drives verification sign-off and coverage closure. Collaborates with architecture, design, firmware, and validation teams, supports silicon bring-up, mentors junior engineers, and improves verification methodologies.

Own full-cycle talent acquisition for specialized semiconductor and FPGA engineering roles, initially supporting India and later global sourcing needs. Develop passive-candidate sourcing strategies using Boolean, X-ray, headhunting, technical communities, referrals, and AI/ML tools. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and build global engineering talent pipelines.

Verify IP blocks and full-chip FPGA/ASIC designs by creating test plans, SystemVerilog/UVM testbenches, stimuli, assertions, reference models, and functional coverage. Debug failures, run regressions, and support verification signoff while collaborating with architects, RTL designers, DFX engineers, and automation teams.

Lead functional verification for complex FPGA/ASIC IPs, subsystems, and SoC features through tape-out. Develop SystemVerilog/UVM environments, test plans, assertions, scoreboards, coverage models, and regression strategies. Debug RTL, gate-level, low-power, and system-level simulations; drive coverage closure and verification sign-off; collaborate with architecture, design, firmware, and validation teams; support silicon bring-up; and mentor junior engineers.

Leads functional verification planning, execution, and sign-off for complex FPGA, ASIC, IP, subsystem, and SoC designs. Develops SystemVerilog/UVM environments, coverage models, assertions, scoreboards, and automation. Drives regression, debug, verification closure, silicon bring-up, and root-cause analysis. Provides technical leadership, mentors engineers, improves verification methodologies, and collaborates with design, firmware, validation, and program teams.

Leads FPGA and ASIC design verification for complex SoC systems, including UVM testbench architecture, coverage-driven testing, protocol verification, subsystem integration, low-power and hardware-software interaction validation, and silicon bring-up. The role manages DV teams, collaborates across design, architecture, software, firmware, and external IP teams, and develops reusable verification methodologies and infrastructure for advanced programmable logic products.

Develop and maintain embedded software for data center solutions from requirements through production and commercial deployment. Design device drivers and upper-layer software stacks, collaborate with silicon design teams on feature development and validation, define software specifications, support quality validation, and debug software issues. The role requires embedded systems, Linux, RTOS, communication protocols, and C/C++ and Python expertise.

Owns architecture, design, validation, bring-up, and production release of high-speed FPGA-based boards. Responsibilities include hardware specifications, schematics, BOMs, signal and power integrity, thermal analysis, component engineering, layout collaboration, debugging, documentation, and cross-functional delivery. The role leads design reviews, mentors engineers, works with suppliers and manufacturing partners, and drives board-development methodology improvements.

Supports adoption and use of FPGA development tools across design entry, synthesis, place-and-route, simulation, and timing closure. Analyzes tool capabilities, documents best practices, delivers training, troubleshoots Linux and tool issues, and improves engineering workflows. Provides ITAR-compliant customer and internal support while serving as an FPGA design-flow subject matter expert. Uses scripting and AI automation tools to improve productivity and tool integration.

Develop embedded software for data center devices from requirements through production and commercial deployment. Design and maintain device drivers and upper-layer software stacks, collaborate with chip design teams on silicon feature development and validation, and work with validation teams to ensure quality. Debug and troubleshoot software issues while supporting embedded Linux, RTOS, communication protocols, and OpenBMC-based solutions.

Design and implement custom and digital semiconductor designs. Develop RTL in Verilog/SystemVerilog, perform transistor-level and schematic work, run simulations and timing/DFT flows, script automation, and support product development and tapeout activities.

Lead design and delivery of connectivity soft IP for Lattice FPGAs: translate specs into high-speed RTL optimized for performance, power, and area; implement/verify SERDES, video and peripheral protocols; perform CDC/lint, timing closure, hardware validation and interoperability tests; develop packaging, example designs and testbenches; provide technical leadership.

Designs and verifies complex FPGA and SoC systems from concept through board-level validation. Develops and optimizes DDR memory controller soft IP, integrates hardened PHYs and peripheral IP, performs timing analysis and constraint writing, evaluates RISC-V systems, and supports hardware validation, interoperability testing, customer issue resolution, and third-party deliverable quality reviews. Leads technical coordination with software, applications, customers, and other stakeholders.

Owns HR data integrity, governance, reporting, dashboards, analytics, and global employment compliance. Builds Workday reports and integrations, audits HR data, manages regulatory calendars and filings, supports audits, and translates workforce data into actionable insights for HR leadership and business stakeholders. The role also coordinates right-to-work processes, immigration-related data, compliance assessments, and reporting infrastructure improvements.

Leads the global Solutions R&D and product lifecycle organization, owning technical strategy, architecture, development, qualification, board design, customer enablement, support, staffing, budgets, and execution. Translates business strategy into semiconductor solutions and revenue-generating products while managing roadmaps, technical standards, quality systems, customer engagements, and multi-site engineering teams across the United States, Malaysia, India, and China.

Leads chip-level power analysis and low-power optimization for FPGA hardware and software. Defines power features, algorithms, user flows, and RTL methodologies; develops power estimation models and benchmarks; correlates simulations with silicon; and influences hardware and software roadmaps. The role uses industry power and timing tools, collaborates across engineering and business teams, and mentors distributed junior engineers.

Develops stand-alone and UVM testbenches, regression suites, coverage dashboards, test plans, and formal equivalence flows for behavioral, functional, and architectural models. Validates models against RTL, schematics, transistor-level designs, and hardware behavior; investigates mismatches, automates verification workflows, resolves integration issues, and reports test status and coverage. Collaborates with IP Design, Verification, Software, Architecture, Integration, and Applications teams.

Support customer evaluation, integration, deployment, and troubleshooting of FPGA-based security and Root-of-Trust solutions. Develop reference designs, firmware examples, application notes, user guides, and technical training. Collaborate with engineering, marketing, technical support, and field applications teams to resolve issues, validate releases, capture customer requirements, and improve security enablement materials.

Leads customer enablement and deployment of FPGA-based security and Root-of-Trust solutions. Provides technical leadership for architecture, integration, troubleshooting, reference designs, documentation, training, and customer engagements. Collaborates across engineering, marketing, technical support, and field applications teams to translate customer needs into product improvements. Requires expertise in FPGA development, embedded C/C++, RTL, cryptography, secure boot, hardware security, and system interfaces, along with the ability to mentor engineers and lead complex technical initiatives.