Jobs at Lattice Semiconductor

Leads end-to-end talent acquisition for specialized engineering roles, including firmware, embedded systems, semiconductor, hardware, infrastructure software, security, and datacenter technologies. Develops sourcing strategies, builds talent pipelines through market mapping and headhunting, partners with engineering leaders on workforce plans, provides talent-market intelligence, and uses AI-enabled recruiting tools and analytics to improve hiring outcomes.

Leads the Pune firmware organization responsible for architecture, development, integration, validation, security, release, and lifecycle management of multiple firmware stacks. Establishes secure development and compliance processes, drives pre- and post-silicon bring-up, collaborates with ASIC, FPGA, verification, security, and product teams, and partners with customers and infrastructure vendors. Recruits and develops engineering talent, reports program status to executives, and applies generative AI to improve engineering productivity.

Manages full-cycle technical recruiting for engineering and technology roles, including sourcing, talent mapping, candidate screening, interview coordination, stakeholder advising, offer negotiation, onboarding support, compliance, and recruiting analytics. Partners with hiring managers and HR leaders across workforce planning and complex requisitions. Requires strong technical recruiting expertise, Mandarin and English fluency, knowledge of Taiwan employment practices, and experience with recruiting systems such as Workday and LinkedIn Recruiter.

Own the solution architecture and behavioral definition of a BIOS/UEFI firmware stack aligned with OCP specifications, including MMBI, OBMF, and mPnP. Represent the company in standards workgroups, translate specifications into implementable architecture and interface documents, and develop technical diagrams, state machines, and integration guides. Collaborate with firmware, engineering, validation, OEM, and ODM teams while supporting technical customer discussions and informing product strategy.

Lead customized UEFI BIOS feature development for CSP and OEM server platforms. Responsibilities include BIOS architecture, platform porting and maintenance, system-level debugging, performance tuning, compatibility resolution, project delivery, and on-site customer support. The role requires approximately five years of UEFI BIOS experience, strong C programming, server architecture knowledge, familiarity with Intel and AMD platforms, and understanding of protocols including PCIe, USB, ACPI, SMBIOS, Redfish, and IPMI.

Develops and integrates UEFI BIOS features for Lenovo desktop and workstation projects, maintains and ports BIOS modules across Intel and AMD platforms, troubleshoots BIOS issues and compatibility problems, and provides on-site customer support. Requires expertise in UEFI architecture, C programming, x86 platforms, BIOS debugging, and protocols including PCIe, USB, and ACPI.

Develop and architect Lattice’s FPGA EDA toolchain, including synthesis, place and route, and timing analysis. Collaborate across engineering teams to deliver a standards-compliant, reliable, and high-performance tool suite. Translate marketing requirements into technical specifications, own specification and planning processes, improve development methodologies, and lead projects and technical discussions.

Drive cross-functional FPGA silicon, Soft-IP, hardware, and software programs through architecture, design, verification, validation, qualification, and release. Manage scope, schedules, resources, risks, reporting, requirements, dependencies, and issue resolution while aligning global engineering, operations, marketing, and executive stakeholders. Translate product requirements into execution plans and ensure timely, high-quality delivery.

Leads cross-functional delivery of datacenter, AI infrastructure, rack management, and platform solutions from concept through deployment and production. Owns program planning, dependencies, risks, executive visibility, customer escalations, lifecycle governance, release readiness, and portfolio execution. Partners with hyperscalers, OEMs, ODMs, and engineering teams to define requirements, resolve system-level challenges, and shape future solution roadmaps.

Architects firmware solutions for Edge AI, drives technical strategy, leads complex design and integration across projects, mentors engineers, collaborates with hardware and software teams, conducts code reviews, and ensures system scalability, reliability, and performance. The role requires extensive embedded firmware experience, strong C/C++ and RTOS expertise, hardware-software co-design experience, and technical leadership.

Develop and maintain large-scale FPGA EDA software and infrastructure using C++. Build capabilities for next-generation FPGA products, support existing design tools, improve development processes, and contribute to specifications and testing. The role focuses on advanced security flows, including isolation design and partial reconfiguration, while requiring cross-functional collaboration and technical leadership.

Designs and develops application-specific IP, integrates IP into SoCs, validates implementation flows, performs SoC-level functional verification and performance evaluation, and establishes board-level boot environments. Collaborates with software engineers on hardware-software co-verification and system debugging. The role requires FPGA, embedded SoC, digital design, Verilog/SystemVerilog, simulation tools, and system bus expertise.

Lead global supply chain strategy and operations for semiconductor products, overseeing demand and supply planning, procurement, logistics, supplier relationships, risk mitigation, capacity planning with foundries/OSATs, and continuous improvement of inventory and forecast accuracy.

Integrates semiconductor IPs into full-chip designs using custom and digital design flows. Responsibilities include developing floorplans, behavioral models, synthesized netlists, schematics, density-specific IPs, and sectors; performing synthesis, equivalence, DFT, timing, power, and performance analysis; debugging with cross-functional teams; and conducting tapeout-gating audits including EMIR, NetERC, PDN, SSO, and ESD checks.

Design Verification Engineer responsible for verifying complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, infrastructure, coverage-driven tests, and subsystem environments. Verify IP using protocols such as AMBA, PCI Express, Ethernet, and USB, while supporting low-power, boot-up, power-cycling, and hardware-software interaction verification. Collaborate with design, architecture, software, firmware, and IP teams to improve quality and tape-out readiness.

Designs, implements, and governs enterprise Salesforce solutions across Sales Cloud, Revenue Cloud, sales planning, and compensation management. Translates revenue and sales requirements into scalable architectures, defines data models and integrations, manages technical debt and release impact analysis, and supports an Oracle CX-to-Salesforce migration. Partners with business stakeholders, product owners, and delivery teams while applying hands-on expertise in Apex, LWC, Aura, Visualforce, Salesforce Flow, APIs, and middleware.

Designs, implements, and governs enterprise Oracle Fusion solutions across Finance and Supply Chain. Evaluates and replaces legacy Oracle EBS customizations with standard Fusion capabilities, architects integrations using OIC and APIs, leads EBS-to-Fusion transformation and data migration, and guides system integrators and implementation teams. The role also designs scalable architectures for future acquisitions, applies Fusion AI and RPA, and oversees reporting, security, analytics, and cloud extensions.

Supports semiconductor product engineers by setting up, operating, troubleshooting, maintaining, and validating ATE and bench test environments. Executes silicon validation, characterization, qualification, and production testing; analyzes yield and performance metrics; manages laboratory equipment, samples, calibration, inventory, procurement, and vendor support. Performs board rework and fixture repair while ensuring ESD compliance, equipment reliability, safety, and continuous laboratory improvement.

Develops ATE test and characterization programs for semiconductor chip IP, executes wafer- and package-level testing, analyzes statistical results, and defines datasheet parameters. Designs test circuits, bench hardware, and automation scripts; investigates product marginalities and drives root-cause resolution. The role also supports sample testing, yield and test-time analysis, and cross-functional collaboration across engineering and applications teams.

Designs, develops, debugs, and ports UEFI firmware to new ARM hardware platforms. Leads board power-on, SoC initialization, platform bring-up, boot-flow, power-sequencing, and memory-initialization activities. Integrates ARM SCP Firmware and Trusted Firmware-A into secure boot chains, collaborates with hardware and silicon teams on low-level issues, uses hardware debugging tools, and documents firmware designs and bring-up procedures.