Jobs at Lattice Semiconductor

Develop constrained-random testbenches and test plans from design specs, implement and execute tests, debug issues, analyze and collate results to closure, and document findings.

Support silicon product enablement for FPGA devices: drive feature enablement, create enablement collateral, provide factory and customer support, run trainings, resolve technical issues, and collaborate with sales and R&D to solidify requirements.

Manage material requirements, monitor WIP and safety stock to prevent production line-downs, coordinate with subcontractors on shipments and lead times, resolve inventory and delivery discrepancies, and collaborate with product planners to optimize inventory.

Design and ship LLM-powered agents to automate code generation, testing, review, and deployment. Collaborate with DevOps, QA, and ML teams to build AI-assisted development toolchains and integrate into CI/CD workflows.

Perform consolidated accounting for Lattice sales offices: month-end close journal entries, account reconciliations, financial review and analysis, SOX compliance and documentation, coordinate external audits, manage local statutory compliance, liaise with third-party accounting and payroll, process Concur reimbursements, and handle ad-hoc accounting tasks. Requires right to work in the Philippines and successful background/reference checks.

Develop and execute Pre-Si and Post-Si test plans for chip IP using FPGA-based test circuits and Lattice design tools. Automate test generation, run ATE and bench validations across process/temperature/voltage, perform root-cause analysis, drive IP content to closure, deliver test content on schedule, and extract coverage metrics using fault grading.

Lead design and development of Lattice FPGA software tools in Penang, focusing on FPGA primitives, Foundation IP and IP catalog tooling. Own release cycle planning, requirement analysis, feature scoping, development, testing and validation. Provide technical leadership, mentor engineers, and ensure delivery quality. Hands-on RTL, testbench, verification, timing closure, device modeling and EDA tool development using C++ and Python.

Lead foundry-facing technical activities to enable process adoption and on-time tape-out. Manage PDK readiness, align design/signoff flows with foundry requirements, define device test structures, support silicon characterization, and scale technology collateral and methodology across teams.

Lead development of connectivity IP for Lattice FPGAs, translating specifications into high-speed RTL designs. Perform RTL design, logic verification, debug, timing closure, and collaborate on validation, soft IP packaging, example designs, and testbenches while mentoring and enabling engineering teams.

Design and implement custom and digital semiconductor designs. Develop RTL in Verilog/SystemVerilog, perform transistor-level and schematic work, run simulations and timing/DFT flows, script automation, and support product development and tapeout activities.

Lead cross-functional FPGA silicon, Soft-IP and software tool programs. Manage scope, schedule, risks, resources, and stakeholder alignment across global teams to ensure timely, high-quality product delivery and executive reporting.

Design and develop analog/mixed-signal IC blocks from specification through post-silicon verification. Perform circuit design and simulation, collaborate on physical layout, integrate analog blocks into digital chips, define bench test plans, perform post-silicon characterization and debug, and mentor junior engineers.

Design, develop, and maintain FPGA software tools and infrastructure; implement features for next-generation FPGA products; support existing tools; produce functional specifications and unit test plans; review marketing requirements; improve development methodologies and collaborate across teams.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Maintain and optimize custom layout CAD flows using Cadence Virtuoso and related EDA tools. Develop automation (SKILL, Python, Tcl, Perl) for handoffs, PDK enablement, libraries, and CI pipelines. Debug tool/flow issues, evaluate EDA quality, collaborate with design and foundry teams, mentor engineers, and support global CAD infrastructure including version control and compute farm tools.

Develop and improve FPGA place-and-route software tools focusing on Isolation Design Flow and QoR (performance, area, runtime, memory). Implement new features, support new FPGA products, write unit tests, collaborate cross-functionally, and support customer needs.

Lead design and optimization of FPGA synthesis engines and toolchains. Drive QoR improvements (Fmax, area, compile time), define architecture and algorithms, modernize codebase, troubleshoot complex synthesis issues, and mentor engineers while aligning features to product roadmap.

Lead design and delivery of connectivity soft IP for Lattice FPGAs: translate specs into high-speed RTL optimized for performance, power, and area; implement/verify SERDES, video and peripheral protocols; perform CDC/lint, timing closure, hardware validation and interoperability tests; develop packaging, example designs and testbenches; provide technical leadership.

Develop and execute comprehensive SoC verification plans and metrics. Build SystemVerilog and C UVM testbenches, UVCs, BFMs and verification tools. Run assertion/formal, directed and randomized tests; perform functional, RTL, assertion and gate-level coverage. Collaborate with design, IP and SW teams to deliver high-quality verification and drive best practices.

Design and execute comprehensive verification plans for SoC/design blocks using SystemVerilog/C UVM testbenches, assertions, formal and directed/random tests. Build verification components, regression environments, perform functional/RTL/assertion/gate-level coverage, and collaborate with design, IP, and software teams to deliver verified silicon on aggressive schedules.