Jobs at Lattice Semiconductor

Own end-to-end design, development, validation, and release of BMC firmware for server platforms. Architect embedded Linux firmware in C, C++, and Python; lead board and silicon bring-up; implement manageability, security, and boot interfaces; troubleshoot complex hardware and software issues; establish testing and quality standards; mentor engineers; document designs; and collaborate with hardware, BIOS, QA, vendors, product teams, and customers.

Own end-to-end talent acquisition for specialized semiconductor engineering roles, initially in India and later supporting global and US sourcing. Develop proactive sourcing strategies for passive technical candidates using Boolean, X-ray, AI/ML, and unconventional channels. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and collaborate on global talent strategies. The role requires deep semiconductor recruiting expertise, strong business acumen, and executive-level communication.

Leads SoC and chiplet-based MCM development from architecture through tapeout and production. Owns chip signoff, system-level modeling, performance tradeoffs, debug, DFx methodology, and hardware design decisions across processor, memory, interconnect, security, configuration, and high-speed interface subsystems. Provides technical leadership across distributed engineering teams, manages IP vendor roadmaps, supports emulation and validation, presents technology strategies to executives, and applies agentic AI to accelerate design execution.

Verify complex FPGA and SoC designs from concept through tape-out using SystemVerilog, UVM, reusable testbenches, coverage-driven testing, and verification plans. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and high-speed protocols, and support low-power, boot-up, power-cycling, and hardware/firmware interaction verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Leads hands-on hardware and firmware QA engineering, including end-to-end functional, integration, system, black-box, grey-box, and non-functional testing. Develops test plans, automation frameworks, scripts, quality gates, and acceptance criteria; performs debugging and root cause analysis. Manages and mentors a QA team, coordinates workloads, reports quality metrics and risks, and drives process improvements. The role also requires developing AI tools for test-case creation and orchestrated test execution.

Develop and maintain OpenBMC firmware features, support platform bring-up, porting, migration, integration, debugging, and upstream changeset adoption. Implement and validate management protocols and hardware interfaces, troubleshoot firmware-hardware issues, and collaborate with platform, hardware, and validation teams through testing and release activities.

Senior individual contributor defining a multi-year edge AI vision and driving hardware-aware model architectures, compiler/ML co-design, and extreme-efficiency techniques across Lattice FPGAs and partner NPUs. Lead ambiguous cross-functional initiatives, build R&D prototypes and model zoo, mentor senior engineers, and align ML strategy with hardware roadmaps and business goals.

Develops, validates, and delivers behavioral and functional models for digital, analog, custom, FPGA, ASIC, and IP hardware. Translates specifications and RTL into model requirements, performs simulation, lint, CDC, regression, equivalency, and quality audits, and resolves hardware-software integration issues. Creates automation and reusable workflows for model generation, validation, release, and reporting. Collaborates across design, verification, software, architecture, integration, and applications teams while providing technical leadership and mentoring.

Lead architecture, RTL development, integration, verification, and productization of high-speed PCIe, USB, MIPI, SerDes, and PHY interface subsystems for FPGA products. Own cross-functional subsystem requirements, coordinate digital, analog, software, package, platform, and validation dependencies, and drive root-cause analysis through silicon bring-up and customer deployment. Engage third-party IP suppliers, manage technical risks, support release readiness, mentor engineers, and improve engineering methodologies.

Develop and modernize software for FPGA flows and hardware-software co-design tools. Responsibilities include refactoring complex legacy C/C++ codebases into modular Modern C++, improving performance and maintainability, implementing automated testing and CI/CD, applying static analysis and code-quality standards, mentoring engineers, guiding architecture and design decisions, and resolving difficult debugging and performance issues. FPGA, EDA, embedded systems, device programming, and hardware-software modeling experience are valuable but not mandatory.

Plans and schedules semiconductor production at external manufacturing partners, translating master production schedules into daily and weekly build plans. Monitors WIP, cycle times, output, schedule adherence, and on-time delivery. Analyzes subcontractor capacity, identifies bottlenecks and material shortages, and coordinates corrective actions. Reports performance KPIs and participates in operations reviews with subcontractors. Requires semiconductor or electronics manufacturing planning experience, strong analytics skills, and knowledge of assembly, bump, and test processes.

Develop and maintain BMC firmware for enterprise and data center servers using C/C++ and Linux. Integrate Redfish, IPMI, MCTP, PLDM, and hardware interfaces with server components including BIOS, CPUs, PCIe, storage, networking, power, thermal, and sensors. Perform firmware bring-up, debugging, optimization, root-cause analysis, automated testing, and customer issue resolution while collaborating with hardware, validation, and systems teams.

Leads full project delivery from presales and requirements scoping through execution, risk resolution, acceptance, and customer follow-up. Coordinates engineering, R&D, QA, sales, and customers; manages project data, metrics, CRM systems, and governance. Oversees team performance and development while standardizing project management practices. Requires strong technical understanding of firmware and source code, customer engagement skills, English communication, and frequent domestic travel.

Manages global HR operations, including Tier 2 and Tier 3 shared-services support, complex Workday transactions, HR compliance, recruiting coordination, sourcing, and candidate communications. Mentors coordinators, maintains SOPs and knowledge bases, improves workflows, monitors data quality, develops reporting, and partners cross-functionally on HR technology and organizational initiatives. The role requires advanced Workday expertise, strong operational judgment, analytical skills, and effective collaboration across HR teams.

Supports global import and export compliance for semiconductor products across multiple countries. Responsibilities include HS and ECCN classification, customs documentation, shipment risk reviews, sanctions and restricted-party screening, permits, end-use assessments, GST compliance, audits, recordkeeping, and coordination with logistics, legal, engineering, and supply chain stakeholders. The role also provides compliance guidance and requires knowledge of semiconductor and dual-use technologies, trade systems, and advanced Excel.

Designs and develops analog and mixed-signal IC circuit blocks from specification and architecture through post-silicon verification. Responsibilities include circuit simulation, physical design coordination, integration into complex digital chips, bench-level test planning, characterization, debugging, and mentoring junior engineers. The role requires advanced analog circuit expertise, FinFET design experience, and proficiency with Cadence AMS tools and methodologies.

Design and develop analog and mixed-signal IC blocks from architecture through post-silicon verification. Responsibilities include circuit simulation, collaboration with mask designers, integration into complex digital chips, post-silicon test planning and debugging, and mentoring junior engineers. The role requires expertise in advanced FinFET technologies, AMS design flows, Cadence tools, and circuits such as SerDes, PLLs, ADCs/DACs, regulators, and clocking systems.

Provide high-level administrative support to the CFO, CHRO, and SVP of Global Operations and their teams, managing complex calendars, coordinating meetings and travel, processing expenses and procurement paperwork, maintaining confidential files, and supporting cross-functional projects, events, and leadership communications.

Lead and support SEC financial reporting, US GAAP technical accounting, monthly/quarterly/annual close, SOX compliance, and operational accounting. Manage audits, mentor accounting staff, drive process and ERP improvements, and partner cross-functionally on acquisitions, stock-based compensation, and other complex transactions for a Nasdaq-listed semiconductor company.

Support silicon product enablement for FPGA devices: drive feature enablement, create enablement collateral, provide factory and customer support, run trainings, resolve technical issues, and collaborate with sales and R&D to solidify requirements.