Jobs at Lattice Semiconductor

Support Intel and AMD BIOS platform porting, bring-up, build verification, boot validation, feature testing, debugging, and issue resolution. Analyze logs and system behavior, contribute to firmware integration and customization, and develop expertise in UEFI BIOS, CPU, memory, PCIe, storage, USB, and platform initialization. Collaborate with global engineering teams through code reviews, technical discussions, and delivery activities.

Develop and maintain BMC firmware for enterprise and data center servers using C/C++ and Linux. Integrate Redfish, IPMI, MCTP, PLDM, hardware interfaces, and server components. Perform firmware bring-up, debugging, optimization, root-cause analysis, automated testing, and customer issue resolution while collaborating with hardware, BIOS, validation, and systems teams.

Design and develop DSP-centric FPGA foundation IP and tooling: create RTL (VHDL/Verilog/SystemVerilog) for DSP macros and programmable DSP slices, run functional simulation and timing analysis, collaborate with software/tools teams, maintain and improve test coverage and product quality across the FPGA toolchain.

Assists with UEFI firmware development, testing, debugging, porting, and integration for ARM-based hardware platforms. Supports board bring-up, power-on validation, hardware debugging, and system-level troubleshooting in collaboration with hardware, silicon, and software teams. Contributes to integrating and validating ARM Trusted Firmware-A and related boot firmware components under the guidance of senior engineers.

Design, develop, debug, port, and bring up UEFI firmware on new ARM hardware platforms. Lead board power-on, SoC initialization, boot flow, power sequencing, and memory initialization efforts. Integrate ARM SCP Firmware and Trusted Firmware-A into secure boot chains, collaborate with hardware and silicon teams on low-level debugging, and document firmware designs and bring-up procedures.

Supports the full supplier contract lifecycle, including contract review, risk assessment, redlining coordination, governance, renewals, and compliance. Manages purchase order compliance, accruals, financial commitments, GL coding, reconciliations, invoice exceptions, and audit documentation. Partners with Legal, Procurement, Finance, Accounting, Accounts Payable, FP&A, Engineering, IT, and business stakeholders to ensure supplier contracts are properly administered, financially controlled, and aligned with company policies.

Provides legal support for Lattice’s global operations, with emphasis on subsidiary governance, corporate records, employment and HR matters, cross-border operations, compliance, outside-counsel coordination, and post-acquisition integration. The role partners with business leaders across Asia-Pacific and global functions, develops scalable legal processes and policies, and delivers practical advice on corporate, employment, regulatory, and operational risks.

Drives complex FPGA and semiconductor programs across architecture, design, verification, validation, qualification, and release. Coordinates global engineering, operations, software, hardware, marketing, and silicon teams while managing scope, schedules, resources, risks, requirements, reporting, and issue resolution. Serves as the primary interface among engineering, operations, and business stakeholders, ensuring alignment, accountability, executive communication, and timely delivery of high-quality products.

Develop and maintain BMC firmware for AMD-based enterprise and data center servers. Responsibilities include C/C++ and Linux development, debugging platform power, sensors, drivers, fan control, firmware updates, and server management features. The engineer collaborates with hardware, BIOS, validation, and customer teams; supports IPMI, Redfish, WebUI, kernel, MCTP, and RAID functionality; develops AMD-specific features; and performs root-cause analysis and technical documentation.

Lead design and implementation of high-speed, low-power SRAM and configuration RAM in advanced FinFET/nanometer CMOS. Own architecture, circuit design, schematic simulation and margin verification, layout planning, full embedded memory design flow, characterization, timing, and model generation while collaborating to meet PPA and yield targets for FPGA products.

Integrates semiconductor IPs into full-chip designs using custom and digital design flows. Responsibilities include developing floorplans, behavioral models, synthesized netlists, schematics, density-specific IPs, and sectors; performing synthesis, equivalence, DFT, timing, power, and performance analysis; debugging with cross-functional teams; and conducting tapeout-gating audits including EMIR, NetERC, PDN, SSO, and ESD checks.

Develop, fine-tune, evaluate, optimize, and deploy large language and multimodal models in local, on-premises, edge, and restricted environments. Build scalable training and inference pipelines, integrate models into production APIs, monitor performance and resource usage, and ensure security and compliance. Collaborate with engineering and business teams, define KPIs, document workflows, evaluate emerging AI techniques, and mentor other engineers.

Develop and validate BMC firmware for server platforms using OpenBMC, Yocto, embedded Linux, C/C++, and Python. Support hardware bring-up, sensor and interface enablement, Redfish and IPMI manageability, security features, debugging, testing, documentation, and code reviews. Collaborate with hardware, BIOS, silicon-vendor, and QA teams while learning under senior engineering guidance.

Develop and maintain UEFI BIOS firmware modules for desktop, mobile, and server platforms. Troubleshoot issues, define and implement features, support releases and customer projects, and port modules across Intel and AMD platforms. Provide customer-requested on-site support and assist with BIOS debugging, maintenance, and adaptation for major OEM systems.

Develop and integrate UEFI BIOS firmware across Intel, AMD, and Arm platforms. Enable new silicon from early bring-up through production, debug boot and hardware issues, implement platform interfaces, optimize reliability, and collaborate with silicon vendors, hardware teams, validation engineers, and customers. The role also involves schematic analysis, low-level debugging, technical documentation, and firmware security improvements.

Leads semiconductor manufacturing test engineering and sustaining activities across OSATs in Malaysia, Taiwan, and Manila. Manages engineers, test capacity expansion, ATE test programs, yield improvement, production support, test setup bring-up, and engineering-to-high-volume manufacturing transitions. Owns product cost and test capacity roadmaps, optimizes test time and flows, addresses test escapes and yield excursions, and collaborates with manufacturing planning and product development teams.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Drive strategy, roadmap, and go-to-market for FPGA IP solutions. Define product/IP requirements, develop MRDs/PRDs, partner with engineering and sales, enable launches, analyze market and customer feedback, and support design wins and revenue growth.

Develop financial and operational models for sales forecasting, budgeting, revenue planning, and performance analysis. Build Power BI, Tableau, Salesforce, and Excel dashboards; maintain data governance; conduct predictive and variance analysis; and deliver actionable insights to sales executives. Partner with sales, finance, and IT teams to improve processes, resource allocation, data quality, and revenue outcomes.