Staff Layout Engineer-DPG-LPDDR

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Staff Layout Engineer-DPG-LPDDR at Micron, you will work on innovative memory and storage solutions. These solutions help transform data into intelligence quickly. You will join a dedicated team collaborating to develop world-class products that set industry standards.

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
• Complete high-speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• Build and optimize array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi-byte and multi-channel configurations.
• Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
• Drive layout-aware co-building with circuit designers to meet timing, noise, IR, and EM requirements for mixed-signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
• Apply guidelines for power distribution, grounding, and isolation, including guard rings, deep-N-well usage, decoupling strategies, and domain separation to protect critical analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon-accurate performance of high-speed and analog-intensive LPDDR blocks.
• Support post-layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
• Work in close partnership with architecture, circuit, verification, and silicon debug groups to ensure first-silicon success and high-volume manufacturability of LPDDR products.
• Contribute to PPA optimization with a strong focus on low-power operation, area efficiency, and reliability requirements specific to LPDDR applications.
• Foster a culture of knowledge sharing and continuous improvement, contributing to VXL-compatible layout flows, guidelines, and build reviews that enable first-silicon success.
• Leverage AI/ML knowledge as a benefit to support data-driven optimization, layout automation initiatives, and improved debug and correlation workflows.

Education

• B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering
• M. Tech in Electronics engineering, Microelectronics or VLSI Engineering

About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
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