Staff Engineer - IC Design

Posted Yesterday
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Hyderabad, Telangana, IND
In-Office
Senior level
Hardware • Software
The Role
Design and deliver synthesizable RTL (Verilog/SystemVerilog) for digital IP from spec to tape-out. Meet PPA targets, support synthesis, timing closure, CDC/RDC, integrate IP into SoCs, collaborate with verification and integration teams, support post-silicon debug, and mentor junior engineers.
Summary Generated by Built In

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Role Overview

We are seeking an experienced RTL Design Engineer with 5–15 years of hands-on experience in digital design and IP development. The ideal candidate will have strong expertise in RTL architecture and micro-architecture definition, with experience developing reusable IP for SoC integration.

Exposure to wireless systems (preferably Wi-Fi) and communication/peripheral IP such as SPI, UART, I2C, DMA, etc., is highly desirable.

Key Responsibilities
  • Develop high-quality, synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
  • Drive IP development from specification to tape-out.
  • Ensure designs meet performance, power, and area (PPA) targets.
  • Develop and maintain design documentation (micro-architecture spec, design spec, integration guide).
  • Collaborate with verification teams to develop test plans and debug functional issues.
  • Support synthesis, lint, CDC/RDC, and timing closure activities.
  • Work closely with SoC integration teams for IP integration and bring-up.
  • Support post-silicon validation and debug.
  • Contribute to IP reuse, configurability, and design methodology improvements.
  • Mentor junior engineers 
Required Qualifications
  • Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
  • 5–15 years of experience in RTL design and digital IP development.
  • Strong proficiency in Verilog/SystemVerilog.
  • Solid understanding of:
    • Digital design fundamentals
    • FSM and datapath design
    • Pipelining and performance optimization
    • Clock domain crossing (CDC) and reset domain crossing (RDC)
    • Low-power design concepts
  • Experience with synthesis and timing analysis.
  • Strong RTL and gate-level debugging skills.
  • Familiarity with industry-standard EDA tools (Synopsys/Cadence/Mentor).
  • Experience with AMBA protocols (AXI/AHB/APB).
Preferred Experience
  • Experience developing communication or peripheral IP such as:
    • SPI, UART, I2C/I3C
    • DMA controllers
    • Timers, interrupt controllers
    • Memory controllers
  • Exposure to wireless subsystems, preferably Wi-Fi (IEEE 802.11) architecture or MAC-level understanding.
  • Experience with packet processing or high-speed data path design.
  • Exposure to security/crypto IP is a plus.
  • Scripting knowledge (Python/Perl/TCL).
  • Experience in advanced technology nodes is an advantage.

"Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Benefits & Perks: 

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Equity Rewards (RSUs) 

  • Employee Stock Purchase Plan (ESPP) 

  • Insurance plans with Outpatient cover 

  • National Pension Scheme (NPS) 

  • Flexible work policy 

  • Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Skills Required

  • Bachelor's or Master's degree in Electronics/Electrical Engineering or related field.
  • 5-15 years of experience in RTL design and digital IP development.
  • Strong proficiency in Verilog and SystemVerilog.
  • Solid understanding of digital design fundamentals, FSM and datapath design, pipelining and performance optimization, CDC and reset domain crossing (RDC), and low-power design concepts.
  • Experience with synthesis and timing analysis.
  • Strong RTL and gate-level debugging skills.
  • Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor).
  • Experience with AMBA protocols (AXI, AHB, APB).
  • Experience developing communication or peripheral IP (SPI, UART, I2C/I3C, DMA controllers, timers, interrupt controllers, memory controllers).
  • Exposure to wireless subsystems, preferably Wi-Fi (IEEE 802.11) or MAC-level understanding.
  • Experience with packet processing or high-speed data path design.
  • Exposure to security/crypto IP.
  • Scripting knowledge (Python, Perl, TCL).
  • Experience in advanced technology nodes.
  • Experience mentoring or guiding junior engineers.

Silicon Labs Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Silicon Labs and has not been reviewed or approved by Silicon Labs.

  • Affordable Benefits Benefits are portrayed as cost-effective, with references to low premiums and employer contributions that make coverage feel financially manageable. This affordability can increase the perceived value of total rewards even when base pay is viewed as merely competitive.
  • Healthcare Strength Healthcare offerings are described as comprehensive, spanning medical, dental, and vision coverage plus mental-health resources. Additional mechanisms like HSA/FSA options and preventive-care coverage reinforce the sense of strong health support.
  • Retirement Support Retirement support appears meaningful, with mentions of a 401(k) match and immediate vesting in some descriptions. Profit-sharing elements are also cited alongside retirement programs, strengthening the longer-term rewards picture.

Silicon Labs Insights

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The Company
HQ: Austin, TX
1,900 Employees
Year Founded: 1996

What We Do

We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

Why Work With Us

Our incredibly talented team is comprised of innovative risktakers pushing the bounds of what’s possible. We’re problem solvers first, addressing the industry’s biggest challenges to transform industries, grow economies and improve lives.

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