ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation, unlocking new levels of productivity and design quality.
Role OverviewWe’re hiring an STA/Timing ClosureLead to develop solutions for closing timing on multi-billion instance ICs and 3D ICsYou’ll work with R&D to define the product architecture and refine the solution at our customer sites.
Key ResponsibilitiesDesign our approach to timing closure for very large designs and 3D ICs with the R&D team.
Run backend and timing flows with customers and use what you learn to improve the product.
Share customer feedback with research and product teams to help set priorities.
Act as our in house expert on STA and timing closure.
BS or MS in Electrical Engineering, Computer Engineering, or a related field.
10+ years running STA and timing closure at a tier 1 design houses.
Experience closing timing at advanced process nodes.
Strong hands on experience with commercial synthesis and timing tools such as Design Compiler and Fusion Compiler.
Deep knowledge of STA, Liberty formats, and device characterization.
Background in device physics at advanced nodes.
Experience with die to die or chiplet to chiplet timing closure.
Experience closing timing on 3D ICs, including TSV design and interconnect timing.
Interest in working directly with customers and shaping the product.
Experience with the broader implementation flow, including place and route.
Experience using AI coding agents such as Claude Code, Codex, or OpenCode.
Scripting experience in Python, Tcl, or Makefiles.
Use your timing expertise to build AI tools for some of the largest chips being designed today.
Work with a strong technical team and an advisory board of EDA veterans, with a product already used by real customers.
ChipAgents is an equal opportunity employer. We welcome applicants of all backgrounds.
What We Offer$180K/yr – $350K/yr base salary + equity. Open to above-scale compensation for exceptional candidates.
Unlimited PTO and full benefits (medical, vision, dental, 401k).
Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.
Skills Required
- BS or MS degree in Electrical Engineering, Computer Engineering, or a related field
- 10+ years running static timing analysis and timing closure at Tier 1 design houses
- Experience closing timing at advanced process nodes
- Hands-on experience with commercial synthesis and timing tools, including Design Compiler and Fusion Compiler
- Deep knowledge of static timing analysis, Liberty formats, and device characterization
- Background in device physics at advanced process nodes
- Experience with die-to-die or chiplet-to-chiplet timing closure
- Experience closing timing on 3D ICs, including TSV design and interconnect timing
- Interest in working directly with customers and shaping the product
- Experience with broader implementation flows, including place and route
- Experience using AI coding agents such as Claude Code, Codex, or OpenCode
- Scripting experience in Python, Tcl, or Makefiles
What We Do
ChipAgents is revolutionizing the chip design and verification process with agentic AI tools tailored for the semiconductor industry. Our flagship product, ChipAgents, leverages advanced AI agents to streamline and enhance the design, debugging, and verification of RTL (Register Transfer Level) code, accelerating time-to-market for chip developers. We are committed to empowering hardware design and verification engineers by providing cutting-edge solutions that improve efficiency, scalability, and accuracy in chip development. Based in Santa Barbara, CA, Alpha Design AI is at the forefront of AI innovation in electronic design automation (EDA).
.png){kind=logo}
